用FPGA实现高效脉冲神经网络，省电又快。
An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- 用位运算替代乘法，降低计算开销。
- 内存减少16倍，MNIST准确率达97.0%。
- 适合边缘设备实时神经形态推理。
脉冲神经网络（SNNs）具有高能效和事件驱动计算特性，适用于低功耗边缘AI。然而，在FPGA上实现SNN面临计算繁重、内存占用大及灵活性不足的问题。本文提出一种面向时间编码SNN的紧凑型片上系统（SoC）架构，集成RISC-V控制器与事件驱动的SNN核心。通过将权重二值化并用位运算替代乘法，结合脉冲时间排序器筛选活跃脉冲，并跳过无效事件以减少计算量。该架构完全运行在Xilinx Artix-7 FPGA上，使权重内存减少最高达16倍，显著降低计算开销与延迟，在MNIST上达到97.0%准确率，在FashionMNIST上达88.3%。此自包含设计为边缘端实时神经形态推理提供了高效可扩展的平台。
原文摘要 · Abstract (English)
Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.
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