为低并行能力设备设计高效视觉主干网络，提升CPU推理速度与精度平衡。
CPUBone: Efficient Vision Backbone Design for Devices with Low Parallelization Capabilities
- 通过分组卷积和减小核尺寸降低计算量，适配CPU特性。
- 在多种CPU设备上实现最优速度-精度权衡，延迟显著降低。
- 适合移动端、嵌入式等算力受限场景的视觉任务部署。
近期视觉主干架构研究多聚焦于高并行硬件平台的效率优化，涵盖手机及嵌入式AI加速模块等场景。相比之下，CPU无法实现类似并行操作，因此模型需采用兼顾计算量（MACs）与硬件执行效率的设计策略，以实现更高的每秒浮点运算数（MACpS）。为此，本文探究了标准卷积的两种改进：分组卷积与减小卷积核尺寸。二者均显著减少推理所需总MACs，同时保持低延迟的关键在于维持硬件效率。在多种CPU设备上的实验表明，这些改进能有效保留高硬件效率。基于此，我们提出CPUBone，一种专为CPU推理优化的新型视觉主干网络家族。CPUBone在广泛CPU设备上实现当前最优的速度-精度权衡（SAT），并在目标检测与语义分割等下游任务中展现出良好迁移能力。模型与代码已开源：https://github.com/altair199797/CPUBone。
原文摘要 · Abstract (English)
Recent research on vision backbone architectures has predominantly focused on optimizing efficiency for hardware platforms with high parallel processing capabilities. This category increasingly includes embedded systems such as mobile phones and embedded AI accelerator modules. In contrast, CPUs do not have the possibility to parallelize operations in the same manner, wherefore models benefit from a specific design philosophy that balances amount of operations (MACs) and hardware-efficient execution by having high MACs per second (MACpS). In pursuit of this, we investigate two modifications to standard convolutions, aimed at reducing computational cost: grouping convolutions and reducing kernel sizes. While both adaptations substantially decrease the total number of MACs required for inference, sustaining low latency necessitates preserving hardware-efficiency. Our experiments across diverse CPU devices confirm that these adaptations successfully retain high hardware-efficiency on CPUs. Based on these insights, we introduce CPUBone, a new family of vision backbone models optimized for CPU-based inference. CPUBone achieves state-of-the-art Speed-Accuracy Trade-offs (SATs) across a wide range of CPU devices and effectively transfers its efficiency to downstream tasks such as object detection and semantic segmentation. Models and code are available at https://github.com/altair199797/CPUBone.
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