让深度图神经网络在电路分析中更快更省内存
GSR-GNN: Training Acceleration and Memory-Saving Framework of Deep GNNs on Circuit Graph
- 用分组稀疏可逆模块压缩节点表示，减少冗余计算
- 实测内存最高降低87.2%，训练速度提升30倍以上
- 适合大规模芯片设计中的深度图神经网络应用
图神经网络（GNN）在电路分析中展现强大潜力，但扩展到现代大规模电路图时受限于GPU内存和训练成本，尤其对深层模型而言。我们重新审视电路图上的深度GNN，发现可训练的深层架构显著优于浅层结构，从而推动开发高效、领域专用的训练框架。提出分组-稀疏-可逆GNN（GSR-GNN），可在保持数百层深度的同时降低计算与内存开销。该方法结合可逆残差模块与分组稀疏非线性算子，压缩节点嵌入而不损失任务相关特征，并采用优化执行流水线，消除碎片化激活存储并减少数据搬运。在采样的电路图上，GSR-GNN实现最高87.2%峰值内存减少和超30倍训练加速，且相关性指标下降可忽略，使深层GNN适用于大规模EDA工作负载。
原文摘要 · Abstract (English)
Graph Neural Networks (GNNs) show strong promise for circuit analysis, but scaling to modern large-scale circuit graphs is limited by GPU memory and training cost, especially for deep models. We revisit deep GNNs for circuit graphs and show that, when trainable, they significantly outperform shallow architectures, motivating an efficient, domain-specific training framework. We propose Grouped-Sparse-Reversible GNN (GSR-GNN), which enables training GNNs with up to hundreds of layers while reducing both compute and memory overhead. GSR-GNN integrates reversible residual modules with a group-wise sparse nonlinear operator that compresses node embeddings without sacrificing task-relevant information, and employs an optimized execution pipeline to eliminate fragmented activation storage and reduce data movement. On sampled circuit graphs, GSR-GNN achieves up to 87.2\% peak memory reduction and over 30$\times$ training speedup with negligible degradation in correlation-based quality metrics, making deep GNNs practical for large-scale EDA workloads.
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