用视觉语言模型优化芯片布局，显著减少布线长度。
See it to Place it: Evolving Macro Placements with Vision-Language Models
- 不微调VLM，通过进化搜索迭代优化布局区域选择。
- 在10个基准上9次超越现有方法，布线长度最多减少32%。
- 可适配多种布局器，适合芯片设计自动化研究者。
我们提出使用视觉语言模型（VLM）进行芯片版图规划中的宏单元布局，这一复杂优化任务近年来已通过机器学习方法取得进展。由于人类设计师高度依赖空间推理来安排芯片上的组件，我们假设具备强大视觉推理能力的VLM能有效补充现有的基于学习的方法。为此，我们引入VeoPlace（视觉进化优化布局）框架，该框架在无需任何微调的情况下，利用VLM约束基布局器在芯片画布的子区域内的操作。VLM的布局建议通过针对布局质量的进化搜索策略进行迭代优化。在开源基准测试中，VeoPlace在10个基准中的9个上优于最佳现有学习方法，峰值布线长度减少超过32%。我们还证明了VeoPlace可泛化至分析型布局器，在所有8个评估基准上提升了DREAMPlace性能，最高提升达4.3%。该方法为电子设计自动化工具利用基础模型解决复杂物理设计问题开辟了新路径。
原文摘要 · Abstract (English)
We propose using Vision-Language Models (VLMs) for macro placement in chip floorplanning, a complex optimization task that has recently shown promising advancements through machine learning methods. Because human designers rely heavily on spatial reasoning to arrange components on the chip canvas, we hypothesize that VLMs with strong visual reasoning abilities can effectively complement existing learning-based approaches. We introduce VeoPlace (Visual Evolutionary Optimization Placement), a novel framework that uses a VLM, without any fine-tuning, to guide the actions of a base placer by constraining them to subregions of the chip canvas. The VLM proposals are iteratively optimized through an evolutionary search strategy with respect to resulting placement quality. On open-source benchmarks, VeoPlace outperforms the best prior learning-based approach on 9 of 10 benchmarks with peak wirelength reductions exceeding 32%. We further demonstrate that VeoPlace generalizes to analytical placers, improving DREAMPlace performance on all 8 evaluated benchmarks with gains up to 4.3%. Our approach opens new possibilities for electronic design automation tools that leverage foundation models to solve complex physical design problems.
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