用自回归方法毫秒生成可仿真的模拟电路，比传统方法快600倍。
ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning
- 结合图变分自编码器与流匹配模型，通过SPICE评分优化设计
- 仅用8次仿真即达99.9%有效率，比遗传算法少40倍仿真次数
- 采用拓扑感知注意力与候选选择策略，适合快速电路设计需求
本文提出ARCS（自回归电路合成）系统，实现模拟电路的快速生成。该系统在毫秒级内生成完整且可由SPICE仿真的电路设计（含拓扑结构与元件值），远快于基于搜索的方法。其混合流程结合图变分自编码器与流匹配模型，并通过SPICE评分进行筛选。在32种拓扑结构上，仅需8次SPICE仿真即可达到99.9%的仿真有效性（奖励6.43/8.0），相比遗传算法减少40倍仿真次数。单模型推理下，采用拓扑感知图变压器与Best-of-3候选选择，在97ms内实现85%的仿真有效性，比随机搜索快600倍以上。核心技术是将群组相对策略优化（GRPO）引入多拓扑电路强化学习，通过每拓扑优势归一化解决REINFORCE方法中的跨拓扑奖励分布不匹配问题，在仅500步强化学习中提升有效性9.6个百分点（较REINFORCE），且步数减少10倍。语法约束解码通过拓扑感知标记掩码，保证100%结构有效性。
原文摘要 · Abstract (English)
This paper presents ARCS (Autoregressive Circuit Synthesis), a system for amortized analog circuit generation. ARCS produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combines two learned generators, a graph VAE and a flow-matching model, with SPICE-based ranking. It achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution adapts Group Relative Policy Optimization (GRPO) to multi-topology circuit reinforcement learning. GRPO resolves a critical failure mode of REINFORCE, cross-topology reward distribution mismatch, through per-topology advantage normalization. This improves simulation validity by +9.6 percentage points over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking.
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