L-SPINE用低精度计算加速神经形态芯片，让边缘设备实时运行脉冲网络。
L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference
- 采用2/4/8比特统一数据通路，用移位加法替代乘法降低算力需求
- 在FPGA上实现仅459 LUTs、0.39ns延迟，功耗仅4.2mW
- INT2/INT4量化大幅减存且几乎不丢精度，适合边缘部署
脉冲神经网络（SNNs）为节能的边缘智能提供了前景，但其硬件部署受限于内存开销大、缩放操作效率低和并行度不足。本文提出L-SPINE，一种面向资源高效边缘推理的低精度SIMD脉冲神经计算引擎。该架构采用统一多精度数据通路，支持2比特、4比特和8比特运算，利用无乘法器的移位加法模型实现神经元动态与突触累积。在AMD VC707 FPGA上实现的单个神经元仅需459 LUTs和408 FFs，关键路径延迟0.39纳秒，功耗4.2毫瓦。系统级指标为46.37K LUTs、30.4K FFs、2.38毫秒延迟、0.54瓦功耗。相比CPU与GPU平台，推理延迟从秒级降至毫秒级，能效提升达三个数量级。量化分析表明，INT2/INT4配置可显著降低内存占用，且精度损失极小。这些结果确立了L-SPINE在实时边缘SNN部署中的可扩展性与高效性。
原文摘要 · Abstract (English)
Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient scaling operations, and limited parallelism. This work proposes L-SPINE, a low-precision SIMD-enabled spiking neural compute engine for efficient edge inference. The architecture features a unified multi-precision datapath supporting 2-bit, 4-bit, and 8-bit operations, leveraging a multiplier-less shift-add model for neuron dynamics and synaptic accumulation. Implemented on an AMD VC707 FPGA, the proposed neuron requires only 459 LUTs and 408 FFs, achieving a critical delay of 0.39 ns and 4.2 mW power. At the system level, L-SPINE achieves 46.37K LUTs, 30.4K FFs, 2.38 ms latency, and 0.54 W power. Compared to CPU and GPU platforms, it reduces inference latency from seconds to milliseconds, achieving an up to three orders-of-magnitude improvement in energy efficiency. Quantisation analysis shows that INT2/INT4 configurations significantly reduce memory footprint with minimal accuracy loss. These results establish L-SPINE as a scalable and efficient solution for real-time edge SNN deployment.
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