arXiv:2604.05147cs.CVcs.CR2026-04

在像素级实现加密,防止图像数据泄露。

Lightweight True In-Pixel Encryption with FeFET Enabled Pixel Design for Secure Imaging

  • 用铁电晶体管的极化状态实现像素内对称加密。
  • 加密后模型识别准确率降至不足10%,抗破解能力强。
  • 硬件开销小,适合嵌入式安全成像系统。

在成像流程中确保端到端安全至关重要,因为视觉数据可能在多个阶段被暴露。高级防护要求在像素值出现在任何读出线上之前完成加密。本文提出一种安全像素传感器(SecurePix),这是一种紧凑的CMOS兼容像素架构,利用铁电场效应晶体管的可编程非易失性多域极化状态实现对称密钥的像素级加密。像素与阵列操作在HSPICE中设计与仿真,采用45 nm CMOS工艺设计套件进行版图绘制,最终确认像素间距为2.33 × 3.01 μm²。每个像素的非易失性编程电平定义其模拟传输特性,使光电二极管电压在像素内直接转换为加密模拟输出。全图评估显示,加密后ResNet-18在MNIST上的识别准确率从99.29%降至9.58%,在CIFAR-10上从91.33%降至6.98%,表明对基于神经网络的推理具有强抵抗能力。基于查找表的逆映射可由授权接收方使用相同对称密钥恢复原始数据。根据HSPICE仿真结果,SecurePix实现每像素编程功耗-延迟积为17 μW·μs,每像素感测功耗-延迟积为1.25 μW·μs,展示出低开销的硬件级保护。

原文摘要 · Abstract (English)

Ensuring end-to-end security in image sensors has become essential as visual data can be exposed through multiple stages of the imaging pipeline. Advanced protection requires encryption to occur before pixel values appear on any readout lines. This work introduces a secure pixel sensor (SecurePix), a compact CMOS-compatible pixel architecture that performs true in-pixel encryption using a symmetric key realized through programmable, non-volatile multidomain polarization states of a ferroelectric field-effect transistor. The pixel and array operations are designed and simulated in HSPICE, while a 45 nm CMOS process design kit is used for layout drawing. The resulting layout confirms a pixel pitch of 2.33 x 3.01 um^2. Each pixel's non-volatile programming level defines its analog transfer characteristic, enabling the photodiode voltage to be converted into an encrypted analog output within the pixel. Full-image evaluation shows that ResNet-18 recognition accuracy drops from 99.29 percent to 9.58 percent on MNIST and from 91.33 percent to 6.98 percent on CIFAR-10 after encryption, indicating strong resistance to neural-network-based inference. Lookup-table-based inverse mapping enables recovery for authorized receivers using the same symmetric key. Based on HSPICE simulation, the SecurePix achieves a per-pixel programming power-delay product of 17 uW us and a per-pixel sensing power-delay product of 1.25 uW us, demonstrating low-overhead hardware-level protection.

像素加密铁电晶体管安全成像低功耗

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