用AI友好的语言设计硬件，自动防错并生成安全代码
Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design
- 用类型系统定义时钟和复位，编译时自动检查跨时钟域等错误
- 自动生成可验证的SystemVerilog代码，428/431个测试通过
- 支持大模型直接根据自然语言描述生成正确硬件代码
我们提出Arch（AI原生寄存器传输时序硬件），一种用于微架构建模与AI辅助代码生成的硬件描述语言。Arch提供流水线、有限状态机、FIFO、仲裁器、寄存器文件、带握手通道的总线、跨时钟域及多周期线程等一等结构，这些在现有HDL中仅能通过易出错的用户定义模式表达。核心设计是将时钟和复位作为参数化类型（Clock<D>, Reset<S,P,D?>），使跨时钟域和复位域分析由外部检查转为编译时类型规则。比特宽、端口方向、单驱动所有权、组合环路等在同一次遍历中追踪，提前捕获锁存器、宽度不匹配、环路和未同步跨时钟等问题。注册声明中的保护条件显式捕捉有效数据模式，防止数据写入前有效标志已置位的错误。每个语法选择都遵循AI可生成性契约：LL(1)文法、无预处理器、统一声明模式、命名块结束、todo!逃生机制，使大模型无需微调即可从自然语言规范生成结构正确、类型安全的Arch代码。编译器输出符合IEEE 1800-2017标准的SystemVerilog，自动生成安全属性（如FIFO不溢出、计数器范围、状态机合法状态、握手协议）并通过Verilator（assert和EBMC）及arch formal工具进行直接AST到SMT-LIB2有界模型检测。集成仿真器将设计编译为原生C++，支持Python cocotb。案例研究：L1缓存和AXI DMA（Yosys/OpenSTA, Sky130）；VerilogEval和CVDP上428/431个测试通过。
原文摘要 · Abstract (English)
We present Arch (AI-native Register-transfer Clocked Hardware), a hardware description language for micro-architecture specification and AI-assisted code generation. Arch provides first-class constructs for pipelines, FSMs, FIFOs, arbiters, register files, buses with handshake channels, clock-domain crossings, and multi-cycle threads -- structures that existing HDLs express only as user-defined patterns prone to subtle errors. A central design choice is that clocks and resets are parameterized types (Clock<D>, Reset<S,P,D?>) rather than ordinary nets, converting CDC and reset-domain analysis from external linter passes into compile-time typing rules. Bit widths, port directions, single-driver ownership, and combinational acyclicity are tracked in the same pass, catching latches, width mismatches, loops, and unsynchronized crossings before simulation. A guard clause on reg declarations captures the valid-data pattern declaratively, catching the producer bug where a valid flag asserts before data is written. Every syntactic choice is governed by an AI-generatability contract: an LL(1) grammar, no preprocessor, a uniform declaration schema, named block endings, and a todo! escape hatch let LLMs produce structurally correct, type-safe Arch from natural-language specs without fine-tuning. The compiler emits lint-clean IEEE 1800-2017 SystemVerilog and auto-generates safety properties (FIFO no-overflow, counter range, FSM legal-state, handshake protocol) verified with Verilator -- assert and EBMC, plus direct AST-to-SMT-LIB2 bounded model checking via arch formal. An integrated simulator compiles designs to native C++ with Python cocotb support. Case studies: L1 cache and AXI DMA (Yosys/OpenSTA, Sky130); 428/431 tests pass on VerilogEval and CVDP.
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