用大模型生成可解释的模拟电路尺寸公式，自动校准跨工艺节点
A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations
- 大模型从网表生成可追溯设计理由的可读公式
- 单次直流仿真校准，2-7次仿真即收敛，误差反馈补偿精度
- 无需重训练即可跨40/90/180纳米工艺直接使用
我们提出一种模拟电路尺寸设计自动化框架，从原始电路网表生成拓扑相关的校准解析公式。大语言模型（LLM）推导出完整的可执行Python尺寸函数，每个器件尺寸均可追溯至具体设计依据，实现现有优化与基于大模型方法中缺失的可解释性输出。确定性校准环路通过一次直流工作点仿真提取工艺相关参数，预测误差反馈机制补偿解析误差。框架在包含两阶段米勒补偿、电流镜、折叠共源共栅、嵌套米勒补偿及互补类AB输出等拓扑的8至30晶体管电路上验证，覆盖40纳米、90纳米、180纳米三个工艺节点。在匹配规格基准测试中，包括类AB运放案例，框架在2-7次仿真内完成收敛。尽管初始预测误差较大，收敛依赖于测量反馈架构而非预测精度。一次性校准自动捕获工艺相关变化，实现无需修改、重训练或每工艺特性化即可跨工艺节点移植。
原文摘要 · Abstract (English)
We present a design automation framework for analog circuit sizing that produces calibrated, topology-specific analytical equations from raw circuit netlists. A large language model (LLM) derives a complete Python sizing function in which each device dimension is traceable to a specific design rationale - a form of interpretable output absent from existing optimization-based and LLM-based sizing methods. A deterministic calibration loop extracts process-dependent parameters from a single DC operating point simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on circuits ranging from 8 to 30 transistors - spanning two-stage Miller-compensated, current-mirror, folded cascode, nested Miller-compensated, and complementary class-AB output topologies - across three process nodes (40 nm, 90 nm, 180 nm). On matched-specification benchmarks, including the class-AB opamp case, the framework converges in 2-7 simulations. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. The one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization.
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