用强化学习自动设计AI芯片，兼顾性能、功耗与面积。
From LLM to Silicon: RL-Driven ASIC Architecture Exploration for On-Device AI Inference
- 将芯片架构设计建模为统一决策过程，联合优化拓扑与微架构。
- 在3nm节点实现每秒2.98万词的推理速度，低功耗模式下功耗低于13毫瓦。
- 适配7个制程节点，无需人工调参，支持异构资源动态分配。
我们提出一种基于强化学习的编译器，联合优化从3nm到28nm工艺节点上的ASIC架构、内存层次结构及工作负载划分。设计空间被建模为包含混合离散-连续动作的单一马尔可夫决策过程，采用统一的功耗-性能-面积（PPA）目标。使用带专家混合门控的软演员-评论家（SAC）算法，探索网状拓扑、每核微架构及算子布局的联合空间。在两个工作负载上验证：Llama 3.1 8B FP16（高性能模式，3nm下达29809词/秒）和SmolVLM（低功耗模式，所有节点下功耗<13 mW，频率10 MHz）。跨7个工艺节点，强化学习自动调整网状规模与每单元配置，包括异构的FETCH、VLEN及内存分配，无需针对节点的手动调优。
原文摘要 · Abstract (English)
We present an RL-driven compiler that jointly optimizes ASIC architecture, memory hierarchy, and workload partitioning for AI inference across 3nm to 28nm. The design space is formulated as a single Markov Decision Process with mixed discrete-continuous actions and a unified Power-Performance-Area (PPA) objective. Soft Actor-Critic (SAC) with Mixture-of-Experts gating explores the joint space of mesh topology, per-core microarchitecture, and operator placement. We validate on two workloads, Llama 3.1 8B FP16 (high-performance mode, 29809 tokens per second at 3nm) and SmolVLM (low-power mode, less than 13 mW at all nodes, 10 MHz). Across 7 process nodes, the RL automatically adapts mesh sizes and per-tile configurations, including heterogeneous FETCH, VLEN, and memory allocation without node-specific manual retuning.
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