用大模型加速标准单元拓扑优化，提升设计效率与可布线性。
TOPCELL: Topology Optimization of Standard Cell via LLMs
- 将拓扑搜索转化为生成任务，利用大模型实现高效探索。
- 在7nm库生成中实现85.91倍速度提升，布局质量媲美穷举法。
- 零样本泛化能力强，适合先进制程的自动化设计流程。
晶体管拓扑优化是标准单元设计的关键步骤，直接影响扩散共享效率和后续布线可行性。然而，随着先进制程下电路复杂度增加，传统穷举搜索方法变得计算不可行。本文提出TOPCELL，一种基于大语言模型（LLMs）的新颖且可扩展的框架，将高维拓扑探索重构为生成任务。采用组相对策略优化（GRPO）微调模型，使其拓扑优化策略符合逻辑（电路）与空间（版图）约束。在面向2nm先进工艺节点的工业流程中，实验表明TOPCELL显著优于基础模型，能发现可布线且物理感知良好的拓扑结构。在7nm库生成任务中，集成至当前最先进自动化流程后，展现出强零样本泛化能力，布局质量接近穷举求解器，同时实现85.91倍的速度提升。
原文摘要 · Abstract (English)
Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup.
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