用知识图谱引导大硬件设计的代码生成，解决大模型易混乱、出错的问题。
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
- 构建以规格书为锚点的知识图谱，显式表达模块层级与接口关系
- 在三个标准规格文档上生成正确RTL，RISC-V处理器案例验证可靠性
- 适合需要高可靠性的自动化硬件设计人员或研究者
大型硬件设计的可综合Verilog生成仍是大语言模型（LLM）面临的重大挑战，因模型难以模仿人类专家在复杂规范与硬件描述语言（RTL）间进行结构化推理的能力。当生成分层Verilog时，LLM常丢失模块间上下文、虚构接口、编造模块间连接，且无法保持结构一致性，而这些缺陷随设计复杂度上升和规范中包含非正式文本、图表等难以直接操作内容而加剧。为此，我们提出VeriGraphi，一个以规格书为锚点的知识图谱驱动的多智能体框架。该框架构建了结构化的知识图谱（HDA），将模块层次、端口级接口、布线语义及模块间依赖作为第一类图实体与关系显式编码。通过多智能体对规格的迭代分析构建此图谱，提供确定性、可机器校验的结构骨架，再由渐进式编码模块在图谱引导下逐层生成伪代码与可综合RTL，确保每级子模块的接口一致性和依赖正确性。我们在美国国家标准与技术研究院（NIST）提供的三份代表性规格文档及其对应实现上评估该框架，并以RV32I处理器为例展示完整流程。结果表明，VeriGraphi可在极少人工干预下实现可靠的分层RTL生成，显著推进了基于大模型的硬件设计，同时保持强功能性正确性。
原文摘要 · Abstract (English)
Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structured reasoning that human experts employ when translating complex specifications into RTL. When tasked with producing hierarchical Verilog, LLMs frequently lose context across modules, hallucinate interfaces, fabricate inter-module wiring, and fail to maintain structural coherence - failures that intensify as design complexity grows and specifications involve informal prose, figures, and tables that resist direct operationalization. To address these challenges, we present VeriGraphi, a framework that introduces a spec-anchored Knowledge Graph as the architectural substrate driving the RTL generation pipeline. VeriGraphi constructs a HDA, a structured knowledge graph that explicitly encodes module hierarchy, port-level interfaces, wiring semantics, and inter-module dependencies as first-class graph entities and relations. Built through iterative multi-agent analysis of the specification, this Knowledge Graph provides a deterministic, machine-checkable structural scaffold before code generation. Guided by the KG, a progressive coding module incrementally generates pseudo-code and synthesizable RTL while enforcing interface consistency and dependency correctness at each submodule stage. We evaluate VeriGraphi on a benchmark of three representative specification documents from the National Institute of Standards and Technology and their corresponding implementations, and we present a RV32I processor as a detailed case study to illustrate the full pipeline. The results demonstrate that VeriGraphi enables reliable hierarchical RTL generation with minimal human intervention for RISC-V, marking a significant milestone for LLM-generated hardware design while maintaining strong functional correctness.
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