用多智能体自动生成测试平台，提升低数据量下Verilog代码生成效果。
Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
- 通过多智能体协作自动构造测试平台，解决训练数据稀缺问题。
- 在精炼版VerilogEval v2上达到顶尖水平，仅用更少训练数据。
- 适合硬件设计自动化与LLM应用研究者参考。
大语言模型在代码生成方面取得进展，但在硬件描述语言领域仍受限，且训练数据与测试平台常不足。本文提出一种工作流，利用多智能体模型自动生成高质量测试平台，用于高质细调数据的构建。通过自动化测试平台创建，针对规格到Verilog任务的微调模型在精炼版VerilogEval v2基准上表现媲美当前最优方法，同时使用更少训练数据。本研究为基于LLM的HDL生成与自动化验证提供了基础。
原文摘要 · Abstract (English)
Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification.
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