用模拟退火框架优化LLM生成的硬件代码，兼顾功能正确与能效。
HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design
- 将LLM生成的硬件代码作为中间候选，分阶段筛选优化
- 在8个基准上实现更稳定、可重复的功耗性能面积优化
- 适合做硬件自动设计的工程师或研究者参考
大型语言模型（LLMs）在生成寄存器传输级（RTL）硬件设计方面展现出巨大潜力，因其能快速提出多种架构方案。然而，单次生成难以持续产出既功能正确又低功耗的设计。本文提出HYPERHEURIST，一种基于模拟退火的控制框架，将LLM生成的RTL视为中间候选而非最终结果。系统首先通过编译、结构检查和仿真筛选出功能正确的设计，再对通过验证的RTL进行功耗-性能-面积（PPA）优化。在8个RTL基准上的评估表明，该分阶段方法比单次生成的LLM RTL更具稳定性和可重复性。
原文摘要 · Abstract (English)
Large Language Models (LLMs) have shown promising progress for generating Register Transfer Level (RTL) hardware designs, largely because they can rapidly propose alternative architectural realizations. However, single-shot LLM generation struggles to consistently produce designs that are both functionally correct and power-efficient. This paper proposes HYPERHEURIST, a simulated annealing-based control framework that treats LLM-generated RTL as intermediate candidates rather than final designs. The suggested system not only focuses on functionality correctness but also on Power-Performance-Area (PPA) optimization. In the first phase, RTL candidates are filtered through compilation, structural checks, and simulation to identify functionally valid designs. PPA optimization is restricted to RTL designs that have already passed compilation and simulation. Evaluated across eight RTL benchmarks, this staged approach yields more stable and repeatable optimization behavior than single-pass LLM-generated RTL.
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