让AI专用芯片高效运行零知识证明，速度提升十倍。
Enabling AI ASICs for Zero Knowledge Proof
- 将高精度算术转为低精度矩阵运算，消除计算瓶颈。
- 在TPU上实现10倍于现有方案的NTT吞吐量。
- 适合需要高效零知识证明的区块链与隐私计算开发者。
零知识证明（ZKP）验证器成本高昂，主要因多标量乘法（MSM）和数论变换（NTTs）占用大量计算时间。AI ASIC如TPU具备极高的矩阵运算吞吐量和顶尖能效。我们提出MORPH框架，首次将ZKP核心算法适配至AI-ASIC执行。引入大T复杂度（Big-T complexity）模型，揭示传统大O忽略的硬件异构瓶颈与布局转换开销。基于此分析：（1）在算术层面，MORPH设计了以MXU为中心的扩展RNS惰性约简方法，将高精度模运算转化为密集低精度GEMM，彻底消除进位链；（2）在数据流层面，构建统一分片、布局固定的TPU Pippenger MSM与优化的3/5步NTT，避免芯片内数据重排，显著降低内存重组开销。在JAX中实现，MORPH使TPUv6e8在NTT上达到比GZKP高10倍的吞吐量，且在MSM上性能相当。代码开源：https://github.com/EfficientPPML/MORPH。
原文摘要 · Abstract (English)
Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH.
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