用多智能体协作生成更可靠的芯片RTL代码，解决工业级设计难题
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
- 六种专业智能体动态协作，结合符号推理与神经网络提升生成质量
- 在工业级CVDP基准上达到94.7%正确率，比单次生成高出36-60个百分点
- 适合芯片设计自动化、硬件LLM研究者，尤其擅长复杂模块分层构建
大型语言模型在自然语言转寄存器传输级（RTL）代码方面展现出潜力，但单次生成在标准测试集上仅达60-65%功能正确率。多智能体方法如MAGE在VerilogEval上达到95.9%，但在更难的工业基准NVIDIA CVDP上未被验证，缺乏综合意识且API开销高。本文提出ChipCraftBrain，融合符号-神经推理与自适应多智能体编排的自动化RTL生成框架。四大创新包括：(1) 基于PPO策略的六智能体自适应编排，状态维度168（亦评估替代世界模型MPC规划器）；(2) 混合符号-神经架构，算法求解K-map和真值表问题，专用智能体处理波形时序与通用RTL；(3) 基于321个模式库与971个开源实现的知识增强生成，支持聚焦检索；(4) 依赖有序的层次化规格分解与接口同步。在VerilogEval-Human上，平均通过率97.2%（7次运行范围96.15%-98.72%，最佳154/156），媲美ChipAgents（97.4%）并优于MAGE（95.9%）。在涵盖五类任务的302题非智能体版CVDP子集上，平均通过率94.7%（286/302，3次运行平均），每类任务较公开单次基线提升36-60个百分点；在与NVIDIA ACE-RTL共享的四类任务中领先三项，且每次问题尝试次数约为其1/30。一次RISC-V SoC案例研究显示，分层分解成功生成8/8通过Lint检查的模块（689行代码），并在FPGA上验证，而单体生成完全失败。
原文摘要 · Abstract (English)
Large Language Models (LLMs) show promise for generating Register-Transfer Level (RTL) code from natural language specifications, but single-shot generation achieves only 60-65% functional correctness on standard benchmarks. Multi-agent approaches such as MAGE reach 95.9% on VerilogEval yet remain untested on harder industrial benchmarks such as NVIDIA's CVDP, lack synthesis awareness, and incur high API costs. We present ChipCraftBrain, a framework combining symbolic-neural reasoning with adaptive multi-agent orchestration for automated RTL generation. Four innovations drive the system: (1) adaptive orchestration over six specialized agents via a PPO policy over a 168-dim state (an alternative world-model MPC planner is also evaluated); (2) a hybrid symbolic-neural architecture that solves K-map and truth-table problems algorithmically while specialized agents handle waveform timing and general RTL; (3) knowledge-augmented generation from a 321-pattern base plus 971 open-source reference implementations with focus-aware retrieval; and (4) hierarchical specification decomposition into dependency-ordered sub-modules with interface synchronization. On VerilogEval-Human, ChipCraftBrain achieves 97.2% mean pass@1 (range 96.15-98.72% across 7 runs, best 154/156), on par with ChipAgents (97.4%, self-reported) and ahead of MAGE (95.9%). On a 302-problem non-agentic subset of CVDP spanning five task categories, we reach 94.7% mean pass@1 (286/302, averaged over 3 runs), a 36-60 percentage-point lift per category over the published single-shot baseline; we additionally lead three of four categories shared with NVIDIA's ACE-RTL despite using roughly 30x fewer per-problem attempts. A RISC-V SoC case study demonstrates hierarchical decomposition generating 8/8 lint-passing modules (689 LOC) validated on FPGA, where monolithic generation fails entirely.
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