用混合进制双曲旋转CORDIC实现低功耗FPGA sigmoid函数
Hardware-Efficient FPGA Implementation of Sigmoid Function Using Mixed-Radix Hyperbolic Rotation CORDIC
- 基于双曲函数关系，用混合进制CORDIC算法替代传统指数运算
- 仅用835个逻辑单元、零DSP，误差低至4.23×10⁻⁴
- 适合资源受限的边缘设备部署，尤其适用于FPGA嵌入式系统
在资源受限的边缘设备（如现场可编程门阵列，FPGA）上高效部署人工神经网络时，非线性激活函数的硬件实现至关重要。尽管存在指数计算开销，sigmoid函数仍广泛用于概率输出、二分类和循环神经网络中的门控机制。本文提出一种基于混合进制双曲旋转CORDIC（MR-HRC）架构的高效FPGA实现方案。该方法利用sigmoid与双曲正切函数间的数学关系，将输入范围归一化至1，使对应tanh计算在0.5范围内进行，显著改善收敛性能。为兼顾精度与硬件开销，引入结合radix-2与radix-4迭代的改进MR-HRC算法：初始radix-2阶段保障稳定收敛，后续radix-4阶段加速收敛且无需尺度因子补偿。最后通过radix-2线性向量化CORDIC（R2-LVC）对MR-HRC所得双曲正弦与余弦值做除法，获得tanh值。整个架构完全流水化，并在Xilinx Virtex-7 FPGA上采用16位定点表示实现。实验结果表明，该设计仅消耗835个逻辑单元，零个数字信号处理单元（DSP），均方绝对误差仅为4.23×10⁻⁴，优于多个近期相关实现。
原文摘要 · Abstract (English)
Efficient hardware implementation of nonlinear activation functions is a crucial task in deploying artificial neural networks on resource-constrained and edge devices such as Field-Programmable Gate Arrays (FPGAs). The sigmoid activation function is widely used for probabilistic output, binary classification, and gating mechanisms in recurrent neural networks, despite its reliance on exponential computations. This paper presents a hardware-efficient FPGA implementation of the sigmoid activation function using a mixed-radix CORDIC-based architecture. The proposed approach leverages the mathematical relationship between the sigmoid and hyperbolic tangent functions. The input range is normalized to 1, enabling the corresponding tanh computation to operate within a reduced range of 0.5, which significantly improves convergence behavior. To achieve high accuracy with minimal hardware overhead, a modified mixed-radix hyperbolic rotation CORDIC (MR-HRC) algorithm combining radix-2 and radix-4 iterations is introduced. The initial radix-2 stage ensures stable convergence, while the subsequent radix-4 stage accelerates convergence without requiring scale-factor compensation. In the final stage, a radix-2 linear vectoring CORDIC (R2-LVC) is used to compute the hyperbolic tangent by dividing hyperbolic sine and cosine values derived from the MR-HRC algorithm. The entire architecture is fully pipelined and implemented on an FPGA. The design is realized on an Xilinx Virtex-7 FPGA using a 16-bit fixed-point representation. Experimental results demonstrate a significant reduction in hardware utilization, requiring only 835 logic slices with zero DSP usage. Additionally, the design achieves a mean absolute error of 4.23 10^-4, outperforming several recent sigmoid implementations.
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