用大模型从Verilog直接预测电路时序，速度快且无需工具链。
TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
- 分两阶段：先生成轻量时序特征，再回归预测关键指标。
- 在VerilogEval上预测准确率超90%，速度比现有方法快1.3~1.6倍。
- 仅需少量数据即可适配新工艺，适合芯片前端快速迭代场景。
早期、无需工具的后综合时序预测仍是快速RTL迭代的关键障碍。我们提出TimingLLM，一种两阶段检索增强的大语言模型框架，可直接从Verilog代码估计最差负松弛（WNS）和总负松弛（TNS）。第一阶段为微调后的语言模型，充当紧凑的后综合时序预言机，生成路径级到达/需求时间，并归纳为轻量级结构-时序线索（如门类计数、关键路径深度、门类型模式）。第二阶段为基于LLM的回归器，预测WNS/TNS，通过最后一层Transformer块中的学习对角校正向量实现优化，该向量由独立检索库中k个最近邻时序标注模块计算得出。在VerilogEval数据集上，TimingLLM实现R_WNS=0.91（MAPE 12%）和R_TNS=0.97（MAPE 16%），运行速度比之前方法快1.3~1.6倍。训练使用包含6万模块及综合报告的新语料库，将公开发布。一次训练后，仅需对每个新工艺库和PVT角落用1000个标注模块微调小型回归头，即可持续超越最先进基线。
原文摘要 · Abstract (English)
Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estimates worst negative slack (WNS) and total negative slack (TNS) directly from Verilog. Stage 1 is a fine-tuned LLM that acts as a compact post-synthesis timing oracle, producing path-level arrivals/required times that are summarized into lightweight structural-timing cues (e.g., bag-of-gates counts, critical-path depth, gate-type patterns). Stage 2 is an LLM-based regressor that predicts WNS/TNS and applies a learned diagonal steering vector at the last transformer block, computed from the k nearest timing-labeled modules in a disjoint retrieval bank. On VerilogEval, TimingLLM attains R_WNS = 0.91 (MAPE 12%) and R_TNS=0.97 (MAPE 16%) while running 1.3-1.6 times faster than prior methods. Training uses a new 60k-module Verilog corpus with synthesis reports, which we will release. After training once, TimingLLM can be adapted to new technology libraries and PVT corners by refitting only a small regression head on 1000 labeled modules per setting, consistently outperforming state-of-the-art baselines.
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