FlowPlace用流模型加速芯片布局，零重叠且快50倍。
FlowPlace: Flow Matching for Chip Placement
- 用掩码引导生成合成数据，避免随机预训练
- 采样速度提升10-50倍，布局无重叠
- 适合需要高效高质布局的芯片设计人员
芯片布局在物理设计中至关重要。现有基于生成模型的方法存在预训练数据随机、采样时间长、依赖梯度求解导致重叠等问题。本文提出FlowPlace，包含掩码引导的合成数据生成、基于流的高效训练与灵活先验注入，以及硬约束采样实现无重叠布局。在OpenROAD和ICCAD 2015基准上的实验表明，FlowPlace在功耗、性能、面积（PPA）指标上更优，采样效率提升10-50倍，且布局零重叠。
原文摘要 · Abstract (English)
Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.
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