arXiv:2605.01931cs.ITcs.AR2026-05中稿 · publication in IEE…被引 2

用深度学习+专用硬件,让5G信道估计快10倍还省电。

SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation

论文配图:SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation
图 1 · 摘自论文原文
  • 用轻量注意力网络从低分辨率数据重建完整信道矩阵
  • 在FPGA上实现亚毫秒延迟,比GPU快24倍、能效高33倍以上
  • 模型压缩后仍保持高精度,适用于不同移动场景和未见信道

信道估计对5G通信网络至关重要,可优化传输参数并保障高速可靠通信。然而,5G中大规模多输入多输出(MIMO)与毫米波(mmWave)技术的应用,在资源受限的硬件平台下面临严苛时延要求与高精度估计的挑战。为此,我们提出SwiftChannel,一种算法-硬件协同设计框架,将面向硬件的深度学习信道估计算法与专用加速器结合。该方法采用带有无参注意力机制的卷积神经网络,从低分辨率最小二乘(LS)估计中重建全分辨率空间-频率域信道矩阵。进一步通过知识蒸馏、卷积重参数化与量化感知训练组成的多阶段模型压缩流程,大幅减小模型规模且几乎不损失精度。硬件加速器基于高阶综合(HLS)在Zynq UltraScale+ RFSoC FPGA上实现,采用细粒度流水线架构与优化数据流策略。实测显示,该加速器达到亚毫秒级延迟,相比GPU方案提升最高达24倍速度,能效提升超过33倍。大量测试表明,该设计不仅在不同噪声水平与用户移动性下表现稳定,还可泛化至多种未见信道配置,优于现有最优基线。通过算法创新与硬件感知设计的统一,本工作为5G MIMO系统提供了一种面向未来的信道估计解决方案。

原文摘要 · Abstract (English)

Channel estimation is crucial in 5G communication networks for optimizing transmission parameters and ensuring reliable, high-speed communication. However, the use of multiple-input and multiple-output (MIMO) and millimeter-wave (mmWave) in 5G networks presents challenges in achieving accurate estimation under strict latency requirements on resource-limited hardware platforms. To address these challenges, we propose SwiftChannel, an algorithm-hardware co-design framework that integrates a hardware-friendly deep learning-based channel estimator with a dedicated accelerator. Our approach employs a convolutional neural network enhanced with a parameter-free attention mechanism, which effectively reconstructs full-resolution spatial-frequency domain channel matrices from low-resolution least squares (LS) estimates. We further develop a multi-stage model compression pipeline combining knowledge distillation, convolution re-parameterization, and quantization-aware training, resulting in substantial model size reduction with negligible accuracy loss. The hardware accelerator, implementing the compressed model and the LS estimator on FPGA platforms using High-level Synthesis (HLS), features a fine-grained pipeline architecture and optimized dataflow strategies. Tested on a Zynq UltraScale+ RFSoC, the accelerator achieves sub-millisecond latency, providing up to 24x speed-up and over 33x improvement in energy efficiency compared to GPU-based solutions. Extensive evaluations demonstrate that the proposed design generalizes not only across various noise levels and user mobilities, but also to a variety of unseen channel profiles, outperforming state-of-the-art baselines. By unifying algorithmic innovation with hardware-aware design, our work presents a future-proof channel estimation solution for 5G MIMO systems.

5G信道估计硬件加速深度学习

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