AI代理80小时自动生成高效量化推理芯片，性能超预期。
Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours
- 多智能体系统自动设计，基于前沿大模型完成复杂芯片架构
- 生成的VerTQ芯片支持TurboQuant，5129个浮点单元，125MHz运行
- 适合芯片自动化设计、AI加速器研发人员快速验证新架构
随着大模型与工具链的快速演进，大型语言模型代理正以惊人速度提升。在我们之前的工作（2025年12月）中，首次提出“Design Conductor”系统，可在12小时内自主构建一个具备完整Linux支持的五阶段RISC-V CPU。本工作引入基于2026年4月发布前沿模型的多智能体框架，可处理80倍更大的任务，实现更高品质、完全自治的设计。我们评估了系统自动生成的4个设计方案，其中“VerTQ”是针对TurboQuant论文提出的专用推理加速器，采用240周期流水线硬连线支持，包含5129个FP16/32计算单元；该设计在TSMC 16FF工艺下映射至FPGA，频率达125MHz，面积仅5.7mm²，支持8个注意力流水线。我们分析了系统的关键能力及实际表现，包括令牌消耗与局限性。
原文摘要 · Abstract (English)
Driven by a rapid co-evolution of both harness and underlying models, LLM agents are improving at a dizzying pace. In our prior work (performed in Dec. 2025), we introduced "Design Conductor" (or just "Conductor"), a system capable of building a 5-stage Linux-capable RISC-V CPU in 12 hours. In this work, we introduce an updated multi-agent harness powered by frontier models released in April 2026, which is able to handle 80x larger tasks, at higher quality, fully autonomously. Following a brief introduction, we examine 4 designs that the system produced autonomously, including "VerTQ", an LLM inference accelerator which hard-wires support for TurboQuant in a 240-cycle pipeline, starting from the TurboQuant arXiv paper. VerTQ includes heavy compute processing, with 5129 FP16/32 units; the design was mapped to an FPGA at 125 MHz and consumes 5.7 mm^2 in TSMC 16FF (8 attention pipes). We review the key new characteristics that enabled these results. Finally, we analyze Design Conductor's token usage and other empirical characteristics, including its limitations.
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