用大模型自动探索FPGA加速器设计，省时省力。
LLM-Driven Design Space Exploration of FPGA-based Accelerators
- 用大模型驱动的结构化探索生成多种硬件配置
- 在Zynq-7000上实现满足时序与资源约束的设计
- 适合想快速验证FPGA加速器的开发者
为现代人工智能工作负载设计基于现场可编程门阵列（FPGA）的加速器，需面对架构参数、数据流策略和内存层级构成的庞大复杂设计空间，过程耗时且资源消耗大。尽管SECDA方法通过SystemC仿真和FPGA执行实现了加速器的快速软硬件协同设计，但确定最优配置仍需大量人工投入和领域知识。本文提出SECDA-DSE框架，将大型语言模型（LLMs）融入SECDA生态，自动化实现FPGA加速器的设计空间探索（DSE）。该框架包含结构化DSE探索器生成配置，以及基于检索增强生成与思维链提示的LLM堆栈进行推理引导探索，并通过反馈回路支持持续优化的强化微调。我们通过基于高层次综合的初步评估验证了可行性：生成的设计在Zynq-7000 FPGA上满足时序与资源约束。
原文摘要 · Abstract (English)
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.
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