提出端到端加速框架，让二进制幂量化模型在边缘设备更快更省电。
PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
- 设计专用移位处理单元，用位移代替乘法提升效率。
- 在FPGA上实现后，性能最高提升3.6倍，功耗降低78%。
- 支持TensorFlow Lite，适配多种边缘硬件，开源可复现。
二进制幂（PoT）量化能显著压缩深度神经网络（DNN）规模，并将乘法替换为位移操作以加速推理。已有研究显示PoT量化可在图像分类等任务中保持精度，但在资源受限的边缘设备上的表现仍不明确。通用边缘CPU和GPU缺乏对位移操作的优化支持，而定制硬件加速器可通过专用移位处理单元更好利用该特性。然而，现有推理框架对PoT量化模型支持有限，且不同量化策略对硬件设计、性能与能效的影响尚未系统研究。为此，我们提出PoTAcc——一个面向资源受限边缘设备的开源端到端加速与评估框架。该框架通过TensorFlow Lite实现跨异构平台（包括纯CPU与混合CPU-FPGA系统）的无缝部署。针对三种PoT量化方法，我们设计了移位处理单元（shift-PE），并在两个FPGA平台上实现。评估涵盖多种模型（含CNN与Transformer架构），结果表明，在PYNQ-Z2与Kria板上，相比纯CPU执行，我们的CPU-加速器设计最高可实现3.6倍速度提升和78%能耗降低。代码将公开于https://github.com/gicLAB/PoTAcc。
原文摘要 · Abstract (English)
Power-of-two (PoT) quantization significantly reduces the size of deep neural networks (DNNs) and replaces multiplications with bit-shift operations for inference. Prior work has shown that PoT-quantized DNNs can preserve accuracy for tasks such as image classification; however, their performance on resource-constrained edge devices remains insufficiently understood. While general-purpose edge CPUs and GPUs do not provide optimized backends for bit-shift operations, custom hardware accelerators can better exploit PoT quantization by implementing dedicated shift-based processing elements. However, deploying PoT-quantized models on such accelerators is challenging due to limited support in existing inference frameworks. In addition, the impact of different PoT quantization strategies on hardware design, performance, and energy efficiency during full inference has not been systematically explored. To address these challenges, we propose PoTAcc, an open-source end-to-end pipeline for accelerating and evaluating PoT-quantized DNNs on resource-constrained edge devices. PoTAcc enables seamless preparation and deployment of PoT-quantized models via TensorFlow Lite (TFLite) across heterogeneous platforms, including CPU-only systems and hybrid CPU-FPGA systems with custom accelerators. We design shift-based processing element (shift-PE) accelerators for three PoT quantization methods and implement them on two FPGA platforms. We evaluate accuracy, performance, energy efficiency, and resource utilization across a range of models, including CNNs and Transformer-based architectures. Results show that our CPU-accelerator design achieves up to 3.6x speedup and 78% energy reduction compared to CPU-only execution for PoT-quantized DNNs on PYNQ-Z2 and Kria boards. The code will be publicly released at https://github.com/gicLAB/PoTAcc
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