EULER-ADAS用统一架构实现低功耗高可靠车载推理，支持多种精度灵活切换。
EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
- 采用有界对数正位数表示与流水线自适应乘法，降低计算开销。
- 在FPGA上实现功耗降低71.9%、延迟减少76.1%，能效比提升10倍。
- 适合嵌入式车载系统，实测仅损失1.5%精度，满足实时低功耗需求。
高级驾驶辅助系统（ADAS）需要在严格功耗和面积限制下实现低延迟推理。正位数算术因其在低精度下仍保持高数值保真度而受到关注，但其可变长度的指数域编码会增加编解码开销，并使数据通路易受大指数域故障影响。本文提出EULER-ADAS，一种面向能效与可靠性感知的ADAS加速的SIMD增强型对数有界正位数神经计算引擎。该设计结合有界指数域正位数表示、分阶段自适应对数尾数乘法与位截断，以及支持正位数-(8,0)、(16,1)、(32,2)的SIMD共享累加路径。统一架构实现4倍正位数-8、2倍正位数-16或1倍正位数-32运算，无需重复硬件。FPGA验证显示，相比精确正位数引擎，配置可降低41.4%的查找表用量，延迟减少76.1%，功耗下降71.9%，能效比优于基于radix-4 Booth的正位数乘法器10倍。在28nm CMOS工艺下，有界版本占用0.013–0.016 mm²，功耗19.8–22.1 mW，最高运行频率达1.84 GHz。跨图像分类、ADAS与边缘推理工作负载的应用评估表明，正位数-16与正位数-32配置在精度上仅比FP32低约1.5个百分点。在Pynq-Z2平台部署的TinyYOLOv3原型实现78毫秒延迟、0.29瓦功耗与22.6毫焦/帧能耗，证明EULER-ADAS适用于低功耗实时ADAS推理。
原文摘要 · Abstract (English)
Advanced driver-assistance systems (ADAS) require neural compute engines that deliver low-latency inference under strict power and area constraints. Posit arithmetic is attractive for such accelerators because it provides high numerical fidelity at low precision, but its variable-length regime encoding increases encode/decode cost and exposes the datapath to large regime-field fault effects. This paper presents EULER-ADAS, a SIMD-enabled logarithmic bounded-Posit neural compute engine for energyefficient and reliability-aware ADAS acceleration. The proposed datapath combines bounded-regime Posit representation, stageadaptive logarithmic mantissa multiplication with bit truncation, and a SIMD-shared quire accumulation path supporting Posit- (8,0), Posit-(16,1), and Posit-(32,2) execution. The unified architecture enables 4xPosit-8, 2xPosit-16, or 1xPosit-32 operation without duplicating precision-specific hardware. FPGA implementation shows that the proposed configurations reduce LUT count by up to 41.4%, delay by up to 76.1%, and power by up to 71.9% relative to exact Posit neural compute engines, while achieving up to 10x lower energy-delay product than radix-4 Booth-based Posit multipliers. In 28-nm CMOS, the bounded variants occupy 0.013-0.016 mm2 , consume 19.8-22.1 mW, and operate at up to 1.84 GHz. Application-level evaluation across image-classification, ADAS, and edge-inference workloads shows that the evaluated Posit-16 and Posit-32 configurations remain within about 1.5 percentage points of FP32 accuracy. A TinyYOLOv3 prototype on Pynq-Z2 achieves 78 ms latency at 0.29 W and 22.6 mJ/frame, demonstrating the suitability of EULERADAS for low-power real-time ADAS inference.
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