TREA通过低精度时分复用设计，大幅降低边缘设备目标检测的延迟和功耗。
TREA: Low-precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
- 采用4/8位双精度并行计算单元，支持运行时截断，避免乘法器开销。
- 3×3卷积仅需1周期（4位模式），相比8位模式提速9倍，延迟降低9倍。
- 可重构非线性激活模块支持多种函数，通过时分复用实现硬件高效复用。
本文提出TREA，一种面向边缘视觉任务的低精度、时分复用、资源高效的神经网络加速器，旨在满足边缘设备对面积、功耗与延迟的严苛约束。该架构采用基于最高有效位优先移位相加的双精度（4/8位）单指令多数据（SIMD）乘累加（DQ-MAC）单元，并结合运行时位截断，消除传统乘法器开销，减少累加器位宽。DQ-MAC每周期可执行4次定点4位或1次定点8位运算，无需硬件冗余即可实现最高4倍吞吐量提升。同时，协同设计了结构化硬件感知剪枝（SHARP）策略，在保持全MAC利用率的前提下实现近50%结构化稀疏性。在4位模式下，3×3卷积可在1周期内完成（8位模式需9周期），5×5卷积则从25周期降至3周期，核级延迟最高降低9倍。加速器还集成了可重构的CORDIC型非线性激活函数（RQ-NAF）核心，具备9级流水线，支持Sigmoid、Tanh、ReLU三种函数，填满流水后每周期输出一次结果，且通过时分复用实现（N-1）次硬件复用。完整TREA架构采用100个1维排列的SIMD DQ-MAC单元，结合层间硬件复用，显著降低面积与控制复杂度。实验表明，相较于传统固定精度与不可重构加速器，TREA在延迟、硬件利用率与能效方面均有显著提升，验证其对实时边缘视觉任务的有效性。
原文摘要 · Abstract (English)
This work presents TREA, a low-precision time-multiplexed and resource-efficient edge-AI accelerator for object detection and classification, targeting stringent area-power-latency constraints of edge vision platforms. The proposed architecture integrates a dual-precision (4/8-bit) SIMD multiply-accumulate (DQ-MAC) unit based on most-significant-digit-first (MSDF) shift-and-add computation with run-time bit truncation, eliminating conventional multiplier overhead and reducing accumulator bit-width. The DQ-MAC supports 4x FxP4 or 1x FxP8 operations per cycle, achieving up to 4x throughput improvement without hardware duplication. A structured hardware-aware reductive pruning (SHARP) strategy is co-designed with the SIMD datapath, enabling near 50% structured sparsity while maintaining full MAC utilization. This allows a 3x3 convolution kernel to be computed in 1 cycle in FxP4 mode compared to 9 cycles in FxP8, and a 5x5 kernel in 3 cycles versus 25 cycles, yielding up to 9x latency reduction at the kernel level. The accelerator further incorporates a reconfigurable CORDIC-based nonlinear activation function (RQ-NAF) core with a 9-stage pipeline, supporting Sigmoid, Tanh, and ReLU at one output per cycle after pipeline fill, while enabling (N-1) hardware reuse through time-multiplexing. The complete TREA architecture employs a 1D array of 100 SIMD DQ-MAC units with layer-wise hardware reuse, significantly reducing area and control complexity. Experimental results demonstrate substantial improvements in latency, hardware utilization, and energy efficiency compared to conventional fixed-precision and non-reconfigurable accelerators, validating TREA as an effective solution for real-time edge vision workloads.
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