为嵌入式神经网络设计可重构乘法器，省电超6成。
A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- 在RISC-V核心中集成可动态调节精度的乘法器，支持精确与近似计算
- 在近似模式下功耗降低62%-68%，矩阵乘法能耗低至1.21 pJ/指令
- 适合对能效敏感的边缘人工智能应用，如嵌入式视觉系统
神经网络因在计算机视觉和深度学习中的卓越表现而广泛应用。为在能量受限的嵌入式设备上部署神经网络，需优化其计算效率，但有限的能源构成重大挑战。本文提出一种集成于RISC-V核心的运行时可重构乘法器架构，旨在实现神经网络推理的能效优化与边缘AI应用。该乘法器通过专用mulscr支持精确与近似计算，并提供多级可配置精度，可在标准处理器流水线中实现细粒度能效-精度控制。在精确与近似模式下分别实现44%-52%和62%-68%的功耗降低，同时保持1.89 DMIPS/MHz的计算性能。在误差容忍型任务（如2D卷积、矩阵乘法）上的评估显示，能耗最高降低63%；矩阵乘法能耗达1.21 pJ/指令，验证了其在能源受限边缘AI部署中的有效性。
原文摘要 · Abstract (English)
Neural Networks (NNs) have been widely adopted due to their outstanding efficacy and adaptability across computer vision and deep learning applications. The optimization of NNs is necessary to enable their deployment on energy constrained embedded devices, where the limited available energy poses a significant challenge for efficient inference. This paper presents a runtime reconfigurable multiplier architecture integrated into the RISC-V core, targeting energy efficient neural network inference and edge AI applications. The proposed multiplier supports adaptability for exact and approximate computation with multiple configurable accuracy levels via a dedicated mulscr, enabling fine-grained energy accuracy control within a standard processor pipeline. The proposed design achieves 44%-52% and 62%-68% power reduction in exact and approximate modes respectively, while maintaining the computational performance of 1.89 DMIPS/MHz. Evaluations on error-tolerant workloads including 2d convolution and matrix multiplication demonstrate up to 63% reduction in energy consumption, with the proposed design achieving 1.21 pJ/instruction for matrix multiplication, confirming its effectiveness for energy-constrained edge AI deployments.
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