用机器学习剪枝图结构，让符号加速器更省资源
Machine Learning-Based Graph Simplification for Symbolic Accelerators
- 用随机森林分析历史执行数据，识别并删除低价值节点边
- 在NAPOLY+架构上降低40% FPGA资源占用，提升吞吐与能效
- 兼顾功能正确性验证，适合硬件优化与安全方向研究者
基于图的加速器广泛应用于基因组学、网络安全和人工智能等符号数据处理场景，但常因冗余图结构导致内存过度消耗与效率低下。本文提出AutoSlim，一种基于机器学习的图简化框架，通过提取先前图执行特征并利用随机森林分类器，识别并移除对性能影响小的节点与边。在非确定性有限自动机叠加架构（NAPOLY+）上应用后，AutoSlim将FPGA资源使用量最多降低40%，同时带来吞吐量与功耗效率的提升。框架包含验证环节，确保剪枝后功能等价性，为硬件优化与安全研究提供新方向。
原文摘要 · Abstract (English)
Graph-based accelerators have been widely adopted in symbolic data processing applications such as genomics, cybersecurity, and artificial intelligence. However, these systems often suffer from excessive memory usage and inefficiencies stemming from redundant graph structures. We present AutoSlim, a machine learning-based framework that leverages data-driven methods to prune automata graphs for hardware accelerators. Using features extracted from prior graph executions and a Random Forest classifier, AutoSlim identifies and removes low-impact nodes and edges. When applied to a Non-deterministic Finite Automata overlay architecture (NAPOLY+), AutoSlim reduces FPGA resource usage by up to 40%, with corresponding improvements in throughput and power efficiency. The framework includes a verification step to ensure functional equivalence after pruning and suggests promising directions for both hardware optimization and security.
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