用FPGA加速事件视觉中的对比度最大化算法，实现超快实时运动估计。
FPGA-Based Hardware Architecture for Contrast Maximization in Event-Based Vision
- 基于FPGA设计深度流水线硬件，实现事件流的并行处理
- 相比CPU/GPU提速超200倍，功耗更低
- 适合高速低功耗嵌入式系统，如实时物体追踪
本文提出一种在现场可编程门阵列（FPGA）上实现对比度最大化（CM）算法的硬件架构，用于事件视觉系统。CM通过最大化由异步事件流重构的扭曲图像（IWE）的对比度来估计运动参数。事件视觉传感器生成稀疏、高时间分辨率、低空间冗余的数据，非常适合硬件处理。利用FPGA的确定性与大规模并行特性，设计了深度流水线架构，支持高吞吐、低功耗的实时嵌入式处理。论文详述了事件扭曲、对比度计算和迭代优化等硬件模块，讨论关键实现决策，并提出硬件感知优化方法。实验表明，该架构相较CPU和GPU实现提升显著，运动参数估计速度超过200倍。据我们所知，这是首个实现CM算法硬件加速的架构。性能评估涵盖处理速度、能效与资源利用率。在事件视觉目标追踪应用中验证，结果证明其为高速、低功耗嵌入式系统提供了可靠的实时运动估计基础。
原文摘要 · Abstract (English)
This paper presents a hardware architecture that implements the Contrast Maximization (CM) algorithm in Field-Programmable Gate Array (FPGA) resources for event-based vision systems. CM estimates motion parameters by maximizing the contrast of an Image of Warped Events (IWE) reconstructed from asynchronous event streams. Event-based vision sensors generate sparse data with high temporal resolution and low spatial redundancy, which makes them well suited for hardware processing. The deterministic, massively parallel structure of the FPGA is leveraged to design a deeply pipelined architecture capable of high-throughput, energy-efficient processing suitable for real-time embedded applications. This paper details the hardware modules responsible for event warping, contrast computation, and iterative optimization, discusses key implementation decisions, and presents the hardware-aware optimization method used in the design. Experimental results demonstrate a substantial speed and efficiency improvement over CPU- and GPU-based implementations, with motion parameter estimation executing over 200 times faster. To the best of our knowledge, this is the first hardware architecture enabling acceleration of CM algorithm computations. Its performance is evaluated in terms of processing speed, energy efficiency, and hardware resource utilization. The proposed design is validated using an event-based object tracking application. The results confirm that the architecture provides a solid foundation for real-time motion estimation in high-speed, low-power embedded systems.
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