用多项式区间验证模拟神经网络在工艺波动下的可靠性，速度提升千倍。
Formally Verifying Analog Neural Networks Under Process Variations Using Polynomial Zonotopes
- 基于多项式建模模拟神经元电路的工艺敏感性。
- 验证时间从一天缩短至秒级，覆盖99%变异样本。
- 适合关注芯片级神经网络可靠性的硬件与验证研究者。
模拟神经网络因其在功耗和处理速度上的优势受到关注。然而，由于其作为物理电路实现，对制造工艺波动极为敏感，可能导致与标称模型的显著偏差。本文提出一种基于多项式的模型，模拟神经元电路在工艺波动下的性能表现。通过多项式区间进行可达性分析，实现形式化验证，避免了传统耗时的蒙特卡洛仿真。我们在三个不同数据集及全连接与卷积型模拟神经网络上评估该方法。实验结果表明，该验证方法将验证时间从长达一天缩短至秒级，同时覆盖高达99%的变异样本，有效验证了其可行性与高效性。
原文摘要 · Abstract (English)
Analog neural networks are gaining attention due to their efficiency in terms of power consumption and processing speed. However, since analog neural networks are implemented as physical circuits, they are highly sensitive to manufacturing process variations, which can cause large deviations from the nominal model. We present a polynomial-based model that resembles the performance of the neuron circuit under process variations. This model is formally verified via reachability analysis using polynomial zonotopes, thus avoiding conventional, time-consuming Monte Carlo simulations. We evaluate our proposed verification approach on three different datasets and on fully-connected and convolutional analog neural networks. Our experimental results confirm the effectiveness of our verification approach by reducing the verification time from up to a day to seconds while enclosing up to 99% of the variation samples.
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