LLM赋能硬件设计，但带来新安全风险，本文系统分析机遇与挑战。
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
- 用LLM生成RTL代码并自动化测试用例，提升设计效率。
- 发现数据污染和对抗攻击等严重安全隐患，影响硬件可信性。
- 适合芯片设计、安全研究者参考，尤其关注AI驱动的可信设计。
大型语言模型（LLMs）正快速融入电子设计自动化（EDA）与硬件安全领域，显著提升寄存器传输级（RTL）代码生成、测试平台自动化及高层规格与硅片实现间的语义对齐能力。然而，其引入了严重的安全漏洞。本文系统综述了基于LLM的硬件设计最新进展，涵盖EDA综合、硬件可信性、安全设计及教育四个方向。重点分析了基于推理的合成、多智能体漏洞挖掘、数据污染与对抗机器学习逃逸等关键技术。讨论了动态基准测试以缓解数据记忆化、强化红队测试以提升安全评估鲁棒性等对策。最后总结跨领域经验，为构建安全、可信、自主的硬件设计生态提供指导。
原文摘要 · Abstract (English)
The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry. While LLMs offer unprecedented capabilities in generating Register Transfer Level (RTL) code, automating testbenches, and bridging the semantic gap between high-level specifications and silicon, they simultaneously introduce severe vulnerabilities. This comprehensive review provides an in-depth analysis of the state-of-the-art in LLM-driven hardware design, organized around key advancements in EDA synthesis, hardware trust, design for security, and education. We systematically expand on the methodologies of recent breakthroughs -- from reasoning-driven synthesis and multi-agent vulnerability extraction to data contamination and adversarial machine learning (ML) evasion. We integrate general discussions on critical countermeasures, such as dynamic benchmarking to combat data memorization and aggressive red-teaming for robust security assessment. Finally, we synthesize cross-cutting lessons learned to guide future research toward secure, trustworthy, and autonomous design ecosystems.
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