用生成网络模拟电路故障，评估不同逻辑门失效对系统鲁棒性的影响。
Fault tolerance estimation in digital circuits with visualised generative networks
- 构建GAN模型，通过生成比特配置对比理想与真实信号差异
- 量化各类故障模式（如器件缺失、错位）导致的信号偏差
- 可定位关键薄弱逻辑门，适合电路可靠性设计人员参考
我们提出一种新数值方法，利用生成网络采样技术估算数字电路结构中各类故障模式的容错能力。基于经典逻辑门构成的数字电路设计，从生成的比特配置随机输入出发，将预期输出电流与生成对抗网络（GAN）判别器部分的数值实验真实信号进行比较，计算理想数字信号的偏差，涵盖缺失或互换逻辑器件等各类错误模式。通过对GAN在复数变量下的表示进行分析，可区分不同经典逻辑元件引发的故障影响，从而评估电子设计的鲁棒性。
原文摘要 · Abstract (English)
We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals of a numerical experiment at the discriminator part of the Generative Adversarial Network (GAN) to calculate the deviation from ideal digital electronic signals, including various error modes, such as missing or interchanged logical devices. From the present analysis of a representation of the GAN in terms of complex variables, it is possible to evaluate the robustness in electronic designs by differentiating the impact of failure modes associated with different classical logical elements in the circuit.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。