通过合并多轮执行轨迹，扩展硬件计数器覆盖范围以提升性能预测精度。
Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage
- 基于启发式方法融合不同运行的执行轨迹，整合多组硬件计数器数据。
- 在真实应用上验证，合并后的计数器保持可接受精度，支持更丰富的特征空间建模。
- 适合需要高维硬件特征的高性能计算性能预测研究者使用。
本文提出一种基于启发式的框架，用于扩展高性能计算（HPC）工作负载性能预测中硬件计数器的覆盖范围。由于同时采集的硬件计数器数量有限，传统方法受限于特征维度。为此，我们通过分析MPI结构、时间模式和通信行为，在多个不同计数器配置的执行轨迹间匹配计算爆发段，实现数据融合。该方法构建了一个包含完整计数器集合的合成轨迹，无需依赖计数器复用（multiplexing）。在MareNostrum5系统上的测试表明，所生成的合并计数器在多种核函数和实际应用中保持可接受的准确性，且可直接用于训练机器学习模型，无需预先选择计数器。该方法显著提升了特征丰富度，支持更全面的性能建模。
原文摘要 · Abstract (English)
This work extends a framework for predicting the performance of High-Performance Computing (HPC) workloads using Machine Learning (ML). A common limitation in performance modeling is the restricted number of hardware counters that can be collected simultaneously. To address this, we propose a heuristic-based methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters. Our approach matches computation bursts across executions by analyzing MPI structure, timing, and communication patterns. This process enables the construction of a unified dataset that includes a wider set of hardware features without relying on multiplexing. The output is a new synthetic trace with all merged counters, which can be used both for HPC performance prediction and for conventional performance analysis. The methodology has been validated on MareNostrum5 machine with a range of kernels and real applications. Results show that the merged counters maintain acceptable accuracy depending on the application, and can be directly used to train ML models on a richer feature space without prior counter selection.
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