用无时钟数字电路实现可扩展类脑计算，低功耗高效处理脉冲数据。
Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip
- 基于无时钟数字电路的自适应脉冲动力学，实现可重构神经网络。
- 音频分类任务性能接近传统方法，功耗显著低于传统数字方案。
- 适合需要低功耗、高灵活性的类脑计算场景，无需专用硬件。
我们提出一种基于无时钟（异步）数字电路自主连续演化的脉冲动力学的可扩展类脑架构。该系统在商用现场可编程门阵列（FPGA）上实现，支持可配置兴奋性与抑制性突触权重的布尔脉冲神经元网络。完整的处理流程可高效处理脉冲编码数据，用于解决机器学习任务。在脉冲编码音频分类任务中表现竞争力，具备高速处理能力。功耗显著低于传统数字实现方式，使其成为连接专用模拟类脑系统与通用数字硬件的高效替代方案。本方法确立了无时钟数字硬件在类脑计算中的可行性，为可重构芯片转化为节能准模拟类脑处理器铺平道路。
原文摘要 · Abstract (English)
We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.
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