在FPGA上实现低功耗脉冲神经网络自适应学习
Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks
- 基于FPGA构建脉冲神经网络加速器，支持局部学习规则
- 在多个数据集上达93%准确率，单次推理功耗低于0.1毫焦
- 无需数字信号处理器，适合边缘设备部署
在边缘端部署自适应智能仍面临训练模型计算与能耗过高的挑战。脉冲神经网络（SNNs）提供了一种有前景的替代方案，但实现在设备上的学习需要软硬件协同设计。本文提出SPIKER-LL，一种基于FPGA的SNN加速器，扩展了开源Spiker+推理架构，高效支持STSF局部学习规则。通过针对性的微架构改进，SPIKER-LL在极低开销下完成推理与在线学习。在MNIST、F-MNIST和DIGITS数据集上，最高达到93%准确率，单次推理延迟低于1毫秒，每推理功耗不足0.1毫焦，且无需数字信号处理器（DSP），具备高度可扩展性，适用于边缘FPGA部署。
原文摘要 · Abstract (English)
Deploying adaptive intelligence at the edge remains challenging due to the high computational and energy cost of training neural models. Spiking Neural Networks (SNNs) offer a promising alternative, but enabling on-device learning requires hardware-algorithm co-design. This paper presents SPIKER-LL, an FPGA-based SNN accelerator that extends the open-source Spiker+ inference architecture with efficient support for the STSF local learning rule. Through targeted microarchitectural extensions, SPIKER-LL performs inference and online learning with minimal overhead. Across MNIST, F-MNIST, and DIGITS, it achieves up to 93% accuracy, sub-millisecond latency, and less than 0.1 mJ per inference, while remaining DSP-free and highly scalable for edge-FPGA deployments.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。