通过输入变换缓解乘法器老化，延长芯片寿命。
Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations
- 利用乘法符号不变性，对输入做补码变换以分散晶体管应力。
- 实验显示寿命显著提升，面积和延迟开销可忽略。
- 适合长期运行的AI加速器和高性能处理器设计。
硬件老化对集成电路构成重大挑战，导致性能下降甚至失效。本文聚焦于现代计算系统（如CPU、GPU、FPGA及类阵列型AI加速器）中的核心组件——算术乘法器的老化问题。由于AI工作负载高度依赖乘法运算，会加剧乘法器中负偏压温度不稳定性（NBTI）效应。本文提出一种新颖的老化缓解技术，利用乘法的符号不变性，通过对输入进行选择性补码变换，实现晶体管应力的重新分布，从而减轻NBTI影响。该方法已集成至典型AI加速器——阵列结构中，验证其在高吞吐场景下的有效性。基于Cadence工具的实验表明，与无缓解措施的自然老化基准相比，本方法显著提升了器件寿命，同时引入了可忽略的面积与延迟开销。
原文摘要 · Abstract (English)
Hardware aging poses a significant challenge for integrated circuits (ICs), leading to performance degradation and eventual failure. In this work, we focus on the aging of arithmetic multipliers, which are a cornerstone of modern computing systems including in CPUs, GPUs, and FPGAs, as well as AI accelerators like systolic arrays. In particular, AI workloads, which rely predominantly on multiplications, can accelerate Negative Bias Temperature Instability (NBTI) effects in multipliers. This paper presents a novel aging mitigation technique that leverages the signinvariance property of multiplication. By selectively applying 2s complement transformations to inputs, the method redistributes stress across transistors, reducing the effects of NBTI aging. The proposed method is also integrated into systolic arrays, a common AI accelerator, to demonstrate its efficiency in a high-throughput AI accelerator. Experimental evaluations using Cadence tools show better lifetime compared to natural aging (with no mitigation) baseline, while introducing negligible area and delay overheads.
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