动态调度机器人控制流任务,兼顾延迟与系统稳定。
DAG-Based QoS-Aware Dynamic Task Placement for Networked Multi-Stage Control Pipelines
- 用有向无环图建模多阶段控制流程,动态分配任务位置。
- 在5毫秒内完成切换,端到端延迟降低40%,任务丢失率下降至1.2%。
- 适合对实时性要求高的工业自动化场景,如智能工厂协作机械臂。
当前物理人工智能依赖闭环视觉伺服流程,其感知与规划阶段因嵌入复杂模型而可能在机器人本地产生高计算负荷。实践中,将感知任务静态地卸载到边缘节点,难以满足标准化工业网络下低延迟、高精度的工业场景需求。这凸显了控制-通信-计算(3C)协同设计的重要性:单机全本地执行会压垮加速硬件,而静态边缘卸载则使控制回路暴露于网络抖动。现有自适应任务放置(ATP)控制器仅通过二元阈值规则迁移单一阶段任务,缺乏多阶段模型及显式切换代价建模。本文提出一种基于有向无环图(DAG)的质量服务(QoS)感知动态任务放置(DTP)框架,用于网络化机器人的感知-感知-规划-控制流水线。该流水线被形式化为带有任务级与节点级属性(计算开销、通信延迟、可行部署集合)的DAG;在有限可解释候选集(完全本地、静态卸载、混合)上,基于窗口的代价函数结合尾部端到端延迟、截止时间违反率、硬件利用率及汉明距离切换惩罚,设计具备滞回与最小驻留时间约束的DTP算法,有效抑制任务频繁切换。本文构建理论框架,开展结构化定性分析,并提出两阶段仿真与软硬件在环验证路线。
原文摘要 · Abstract (English)
Current Physical AI (PAI) relies heavily on closed-loop visual-servoing pipelines, whose perception and planning stages may become computationally intensive onboard due to complex models embedded on robots. In practice, offloading the perception task to on-site edges statically is inappropriate for latency-sensitive, precise industrial settings over a standardized industrial network. This emphasizes the importance of Control-Communication-Computing (3C) co-design in industrial automation: monolithic local execution saturates AI-accelerated machine and robot hardware, while static edge offloading exposes the control loop to network jitter. Existing adaptive task placement (ATP) controllers can partially address the gap by relocating a single pipeline stage on binary threshold rules, without a multi-stage model and an explicit cost on placement switching. In this paper, we propose a directed acyclic graph (DAG) based quality-of-service (QoS)-aware dynamic task placement (DTP) framework for sensing-perception-planning-control pipelines in networked robotics. This pipeline is formalized as a DAG with task-level and node-level attributes for compute cost, communication delay, and feasible placement sets; over a small interpretable candidate set (fully local, static offload, hybrid), a window-based cost function combines tail end-to-end latency, deadline violation rate, hardware utilization, and a Hamming-distance switching penalty, and a DTP algorithm with hysteresis and a minimum dwell-time bounds placement chatter. Our work presents the theoretical framework, a structured qualitative analysis, and a two-phase simulation plus hardware-in-the-loop validation roadmap.
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