联合优化量子编译与轻量纠错，提升早期容错系统成功率
Hardware-aware Low-latency Quantum Compilation with Data-driven Lightweight Error Detection for Early Fault-Tolerant Systems
- 硬件感知编译+数据驱动纠错协同优化
- 算法成功率达68%提升，置信区间60%-76%
- 适合追求低延迟高成功率的量子应用开发者
嘈杂中等规模量子（NISQ）处理器正进入早期容错阶段，此时全量子纠错资源开销过大，而轻量级错误检测可显著提升算法成功率。现有编译与纠错工具链各自独立，缺乏在延迟约束下平衡检测开销与成功率的合理机制。本文提出一种集成的硬件感知编译与数据驱动量子错误检测（QED）框架，通过噪声加权代价函数和学习型多目标调度器，联合优化量子比特映射、SWAP插入及校验位调度。基于GPU加速密度矩阵模拟（NVIDIA cuQuantum SDK）在HPC集群上对变分量子本征求解（VQE）、相位估计算法和格罗弗搜索进行测试，涵盖三种噪声模型及6-20量子比特（深度10-160）电路。结果显示，在8量子比特的VQE实例中，结合后选择策略，相比SABRE方法，算法成功率最高提升68%（95%置信区间：60%至76%）。
原文摘要 · Abstract (English)
Noisy intermediate-scale quantum (NISQ) processors are entering an early fault-tolerance regime where full quantum error correction carries prohibitive resource costs, yet lightweight error detection can meaningfully improve algorithmic success rates. Existing compilation and error-detection toolchains treat these concerns in isolation, with no principled way to balance detection overhead against success probability under latency constraints. We present an integrated hardware-aware compilation and data-driven quantum error-detection (QED) framework that jointly optimises qubit mapping, SWAP insertion, and syndrome-schedule placement via a noise-weighted cost function and a learned multi-objective scheduler. Simulation experiments on an HPC cluster using GPU-accelerated density-matrix simulation (NVIDIA cuQuantum SDK) across VQE, phase-estimation, and Grover benchmarks, three noise profiles, and circuit sizes of 6-20 qubits (depths 10-160), show that joint co-design raises algorithmic success probability by up to 68 percent (95 percent CI: 60 percent to 76 percent) over SABRE on an 8-qubit VQE instance with post-selection.
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