SPARX在边缘设备上实现高效低功耗的近似卷积计算，兼顾安全与隐私。
SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC
- 设计近似对数乘法器与定制指令集，提升能效
- 比精确乘法器减少51.7%面积、81.5%功耗，吞吐提升2.13倍
- 支持隐私保护和身份认证，适合部署在资源受限的边缘设备
边缘AI系统需要在严格能源、性能、安全和隐私约束下实现实时卷积神经网络推理。近似计算通过利用神经网络对误差的鲁棒性提升硬件效率，但多数近似加速器未同时考虑安全与隐私。本文提出SPARX框架，集成于异构RV32IMC RISC-V片上系统（SoC），包含定制RISC-V指令扩展、近似对数卷积加速单元、轻量级差分噪声隐私引擎及挑战-响应认证机制。引入近似感知决策框架，基于近似严重度指数（ASI）、近似效率（AE）、近似质量（QoA）、近似性能指标（AFOM）和硬件加速效率（HAE）指导算术选择。在11种先进近似乘法架构中，迭代对数乘法器（ILM）表现最优：相比精确的径向4 Booth乘法器，面积减少51.7%，功耗降低81.5%，吞吐提升2.13倍，仅导致ResNet-20/CIFAR-10准确率下降2.82个百分点。FPGA在Xilinx VC707平台实现58.4 GOPS/W能效，28nm CMOS物理实现验证了ASIC可行性。
原文摘要 · Abstract (English)
Edge-AI systems increasingly require real-time CNN inference under strict energy, performance, security, and privacy constraints. Approximate computing improves hardware efficiency by exploiting the error resilience of neural network workloads; however, most approximate CNN accelerators do not jointly consider secure, privacy-aware edge deployment. This paper presents SPARX, a Secure and Privacy-Aware Approximate CNN Acceleration framework integrated within a heterogeneous RV32IMC RISC-V System-on-Chip (SoC). SPARX combines a custom RISC-V instruction extension, an approximate logarithmic CNN acceleration unit, a lightweight differential-noise-based privacy engine, and a challenge-response authentication mechanism. To guide arithmetic selection, an approximation-aware decision framework is introduced that uses the Approximation Severity Index (ASI), Approximation Efficiency (AE), Quality of Approximation (QoA), Approximation Figure-of-Merit (AFOM), and Hardware Acceleration Efficiency (HAE). Evaluation across 11 state-of-the-art approximate MAC architectures identifies the Iterative Logarithmic Multiplier (ILM) as the most suitable design, achieving 51.7% area reduction, 81.5% power reduction, and 2.13x throughput improvement compared with an accurate radix-4 Booth MAC, while only reducing ResNet-20/CIFAR-10 accuracy by 2.82 percentage points. FPGA implementation on a Xilinx VC707 platform achieves 58.4 GOPS/W energy efficiency at 250 MHz, while 28-nm CMOS physical implementation validates ASIC feasibility
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