将脉冲神经网络部署到FPGA，实现34微秒级低延迟实时推理。
Spiking Neural Network inference on FPGAs with hls4ml
- 基于hls4ml扩展，实现时钟驱动的SNN FPGA部署。
- 在Heidelberg Spiking Digits数据集上达34μs推理延迟。
- 适合需要低延迟实时推理的嵌入式系统开发者。
脉冲神经网络（SNN）提供天然的时间计算框架，其神经元保持内部状态并通过离散脉冲传递信息，实现低延迟的时间推理。尽管SNN常与异步类脑处理器关联，但许多科学实时推理系统仍依赖传统同步FPGA与高层次综合（HLS）工作流。本文提出hls4ml的扩展，支持在FPGA固件上部署用PyTorch训练的量化密集SNN。我们以海德堡脉冲数字数据集上的量化SNN为例，实现约34μs的推理延迟。通过软件参考对比、HLS C仿真、HLS综合、导出及Vivado综合报告验证设计有效性。该工作拓展了hls4ml工具链至类脑计算领域，实现SNN模型的高效优化、综合与部署。
原文摘要 · Abstract (English)
Spiking Neural Networks (SNNs) provide a naturally temporal machine-learning framework. Their neurons maintain an internal state and propagate information through discrete spikes, enabling low-latency temporal inference. Although SNNs are often associated with asynchronous neuromorphic processors, many scientific real-time inference systems rely on conventional synchronous field-programmable gate arrays (FPGAs) and high-level synthesis (HLS) workflows. In this paper we present an extension of hls4ml that enables clock-driven deployment of SNNs trained in pytorch onto FPGA firmware. We demonstrate the workflow using a dense quantised SNN trained on the Heidelberg Spiking Digits dataset where it achieves inference latencies of approximately $34μ$s. We validate the generated design through software reference comparisons, HLS C simulation, HLS synthesis, export, and Vivado synthesis reports. This work opens up the hls4ml toolkit to neuromorphic computing, allowing streamlined optimisation, synthesis, and deployment of SNN models for real-time inference.
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