开源13万条Verilog代码数据集，助力AI生成硬件设计
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
- 整合GitHub、VHDL、C/C++多源Verilog代码，全开放可用
- 用大模型生成配套自然语言描述，支持多种模型微调
- 支持不同量化方式与模型规模对比，适合硬件+AI研究者
OpenRTLSet发布了目前最大的完全开源硬件设计数据集，包含超过13.1万条多样化的Verilog代码样本，供研究界和产业界免费使用。数据集融合来自GitHub的Verilog代码（10.2万模块）、VHDL翻译代码（5千模块）以及可综合C/C++翻译代码（2.4万模块），全部无专利限制。我们利用推理模型DeepSeek-R1为每条代码生成对应的自然语言描述，可用于微调Qwen、Granite等语言模型以实现Verilog代码生成。本研究还探索了多种配置：包括使用Verilator生成的C++文件作为标注上下文、采用INT4与BF16量化技术，以及7B至32B参数量级模型在性能上的差异。结果表明，开源方法在硬件设计任务中可实现优异表现，为该领域的开放研究与商业应用奠定了新基础。
原文摘要 · Abstract (English)
OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our dataset uniquely combines Verilog code from GitHub repositories (102k modules), VHDL translations (5k modules), and synthesizable C/C++ translations (24k modules), all freely accessible without proprietary restrictions. Using the reasoning model DeepSeek-R1, we generated paired natural language descriptions for each code sample, enabling fine-tuning of various language model families (e.g., Qwen and Granite) for Verilog code generation. Our dataset explores multiple options, including Verilator-generated C++ files as additional context during labeling, quantization techniques (INT4 vs. BF16), and performance differences across model sizes (7B-32B parameters). OpenRTLSet demonstrates that open-source approaches can achieve superior performance in hardware design tasks, establishing a new foundation for accessible research and commercial use in this domain.
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