用大模型打通模拟电路设计全流程，从意图到版图只需数小时。
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
- 通过大模型引导拓扑生成与版图约束，实现跨阶段协同设计
- 将设计周期从天/周缩短至小时级，性能更优
- 适合追求高效、精准的模拟电路研发团队
传统模拟电路设计高度依赖人工在拓扑、尺寸和版图阶段的介入，以往自动化方法仅针对单一阶段。本文提出PANDA框架，利用大语言模型（LLM）增强，通过引导式拓扑合成、子结构感知的尺寸优化和约束驱动的版图生成，实现从高层次设计意图到最终版图的端到端贯通。该框架将自动化重心从算法执行转向意图协同设计，使设计周期从数天或数周缩短至数小时，同时提升电路性能。
原文摘要 · Abstract (English)
Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work, we propose PANDA, an LLM-enhanced framework that bridges high-level design intent to final layout by actively managing cross-stage dependencies through guided topology synthesis, substructure-aware sizing, and constraint-driven layout generation. This shifts automation from algorithm-centric execution to intent-centric co-design, reducing turnaround time from days or weeks to hours while improving design performance.
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