用深度学习设计高效功放，兼顾高峰值和回退功率表现。
Deep Learning-Driven Inverse Design of Doherty Power Amplifiers Using Pixelated Combiners and Dual-State Impedance Synthesis
- 结合CNN与像素化布局，用遗传算法优化三端口功放合路器。
- 实测峰值效率超71.2%，6dB回退时效率仍达64%。
- 适合射频芯片设计者参考，尤其关注高能效功放架构。
Doherty功率放大器的输出合路器需在同一网络中实现负载调制、阻抗匹配和相位补偿，设计极具挑战性。本文提出一种三端口合路器设计方法，融合深度卷积神经网络（CNN）、像素化版图表示、遗传算法（GA）与双态阻抗综合技术，以同时优化峰值与回退功率性能。作为概念验证，设计并制作了两款采用三端口像素化合路器的GaN HEMT Doherty PA原型。两款原型均实现测量饱和输出功率超过44.2 dBm，峰值漏极效率高于71.2%，工作频段为2.6–2.8 GHz。此外，在6 dB回退功率下，漏极效率仍达64%。经过数字预失真校正后，每款原型的邻道泄漏比（ACLR）均优于-51.3 dBc。
原文摘要 · Abstract (English)
The output combiner of a Doherty power amplifier (PA) integrates load modulation, impedance matching, and phase compensation within a single network, making its design and synthesis highly challenging. In this paper, we propose a three-port Doherty combiner design methodology that combines deep convolutional neural networks (CNNs), pixelated layout representations, and genetic algorithms (GA) with dual-state impedance synthesis to address both peak and back-off power conditions. As a proof of concept, two GaN HEMT Doherty PA prototypes incorporating three-port pixelated combiners are designed and fabricated. Both prototypes achieve a measured saturated output power exceeding 44.2 dBm with peak drain efficiency above 71.2% within 2.6-2.8 GHz. Furthermore, a drain efficiency as high as 64% is measured at the 6-dB back-off level. After applying digital predistortion, each prototype achieves an adjacent channel leakage ratio (ACLR) better than -51.3 dBc.
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