用LLM+形式化方法生成可解释的硬件代码，确保正确性
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
- 通过迭代应用设计规则，让LLM逐步生成硬件代码
- 生成的RTL代码经验证无逻辑错误，符合设计规范
- 适合需要高可靠性的芯片设计团队使用
大型语言模型在软件开发中表现卓越，但易产生幻觉，引入细微语义和逻辑错误。由于芯片设计与制造风险极高，硬件工程师仍不愿依赖LLM生成寄存器传输级（RTL）代码。本文提出一种结合LLM创造力与形式化方法可解释性、数学严谨性的硬件生成框架。具体而言，设计了一套涵盖多种设计决策与硬件特性的转换规则，通过迭代应用这些规则，使LLM代理能够将设计规范转化为具有保证正确性的RTL程序。实验结果表明该框架在有效性和效率方面均表现出色。
原文摘要 · Abstract (English)
Large language models (LLMs) have achieved remarkable success in software development. However, they are susceptible to hallucinations, meaning that they can introduce subtle semantic and logical errors. Due to the high stakes in chip design and manufacturing, hardware engineers are still reluctant to rely on LLMs for register-transfer level (RTL) generation. In this paper, we propose a hardware generation framework that combines the creativity and broad knowledge of LLMs with the explainability and mathematical rigor of formal methods. Specifically, we devise a set of transformation rules that cover various design decisions and hardware features. By iteratively applying these rules, an LLM agent can convert a design specification into an RTL program with guaranteed correctness. Experimental results demonstrate the effectiveness and efficiency of the framework.
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