用分块推理大幅降低高分辨率图像重建的计算开销。
PatchINR: Patch-Based Implicit Neural Representations for Efficient and Scalable Inference
- 将图像切分为不重叠块，整块预测提升效率
- 2×2块下保持34.97 dB PSNR，延迟降低75%
- 适配FPGA硬件，支持可配置流水线与双精度计算
隐式神经表示（INR）在连续信号建模中表现优异，但传统逐像素推理导致推断次数呈二次增长，在高分辨率场景下计算成本剧增。为此，我们提出基于分块的方法，将非重叠块作为基本处理单元，单次前向传播即可预测整块像素，显著减少推断查询次数。为验证方法有效性，我们在现场可编程门阵列（FPGA）平台上构建了硬件加速架构，具备可配置流水线并支持双精度计算。实验表明，采用2×2分块的分块INR在保持34.97 dB PSNR的同时，推断延迟降低75%，参数量仅增加0.6%。
原文摘要 · Abstract (English)
Implicit Neural Representation (INR) provides an effective approach for continuous signal modeling, but classical per-pixel inference results in quadratic growth in inference count, leading to dramatically increased computational costs in high-resolution application scenarios. To address this issue, we propose a patch-based approach that treats non-overlapping patches as fundamental processing units and predicts entire pixel patches in a single forward pass, significantly reducing the number of inference queries required. To validate the effectiveness of our approach, we propose a hardware acceleration architecture on the Field Programmable Gate Array (FPGA) platform for the INR model, which features a configurable pipeline and supports dual-precision computation. Our patch-based INR achieves comparable reconstruction quality to pixel-level INR (34.97 dB PSNR with 2 x 2 patches) while reducing inference latency by 75% with only 0.6% parameter overhead.
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