让大模型生成NPU高性能代码,避免崩溃和性能下降。
Hawk: Harnessing Hardware-Aware Knowledge for High-Performance NPU Kernel Generation

- 用硬件知识增强大模型,防止生成错误代码。
- 生成准确率从49.4%提升至80.0%,速度最高快2.2倍。
- 适合芯片开发、AI加速器优化方向的研究者。
为神经网络处理器(NPUs)开发高性能内核是行业关键瓶颈,需开发者手动应对隐含的硬件约束与严格的内存层次结构。尽管大语言模型具备强大自动化潜力,但在NPUs上因缺乏硬件特定先验知识而表现灾难性失败。直接复用相似内核代码片段虽可通过编译,却常因无视底层硬件约束导致运行时崩溃与性能下降。为此,我们提出Hawk——一种无需训练的框架,通过三个核心模块融合硬件感知知识:(1) 运行时知识合成模块,采用三部分可执行知识表示,将错误上下文与可执行语义内在耦合;(2) 瓶颈感知知识检索模块,实现二维检索范式,将查询投影至正交的语法与硬件对齐语义空间;(3) 效果驱动知识蒸馏模块,利用大模型驱动的语义仲裁,基于实际执行反馈持续提炼知识,消除错误并整合冗余。在真实NPU工作负载上的大量评估表明,Hawk将生成准确率从49.4%提升至80.0%,同时相较最先进基线实现最高2.2倍的执行加速。
原文摘要 · Abstract (English)
Developing high-performance kernels for Neural Processing Units (NPUs) is a critical industry bottleneck, requiring developers to manually navigate implicit hardware constraints and strict memory hierarchies. While large language models offer immense automation potential, they fail catastrophically on NPUs due to a fundamental lack of hardware-specific priors. Naively transplanting code snippets from similar NPU kernels may pass the compiler, but it consistently triggers runtime crashes and performance degradation by blindly violating underlying hardware constraints. To overcome this, we introduce Hawk, a training-free framework that harnesses hardware-aware knowledge through three core modules: (1) Run-Time Knowledge Synthesis Module, which employs a Triple-Part Executable Knowledge Representation to inherently couple the error context with executable semantics; (2) Bottleneck-Aware Knowledge Retrieval Module, which implements a 2D-Retrieval paradigm to project queries into orthogonal syntactic and hardware-aligned semantic spaces; and (3) Effect-Driven Knowledge Distillation Module, which leverages LLM-driven semantic arbitration to continuously distill the knowledge by pruning errors and consolidating redundancies based on the empirical execution feedback. Extensive evaluations on real-world NPU workloads demonstrate that Hawk elevates generation accuracy from 49.4% to 80.0%, while achieving up to a 2.2x execution speedup over state-of-the-art baselines.
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