优化CPU与存内计算芯片的协同分工，提升边缘设备推理速度。
Optimizing ML Workload Partitioning between CPUs and CIM Accelerators for Heterogeneous Computing
- 用整数规划建模，统筹考虑内存限制和写入延迟等硬件约束。
- 在边缘CPU上实现最高30.9倍加速，高性能CPU上达7.3倍。
- 适合设计存内计算系统或优化异构算力分配的研究者与工程师。
存内计算（CIM）加速器在内存中执行矩阵-向量乘法（MVM），是机器学习工作负载的有力解决方案。然而，现有针对CIM加速器的算力划分方法未充分考虑阻变随机存取存储器（RRAM）的限制，如内存容量有限、写入延迟高及耐久性差等问题，也忽略了并行性、底层架构影响以及中央处理器（CPU）作为互补计算资源的作用。为此，我们提出一种基于整数线性规划（ILP）的异构CPU-CIM系统工作负载划分框架，能在满足RRAM约束的前提下最小化端到端推理延迟，同时捕捉并行性，并结合实测性能分析与解析模型。使用该框架，异构CPU-CIM执行在边缘CPU上相比纯CPU执行获得最高30.9倍加速，在高性能CPU上实现7.3倍加速。设计空间探索（DSE）为未来CIM加速器的设计提供了深入洞察。
原文摘要 · Abstract (English)
Computing-in-Memory (CIM) accelerators execute Matrix-Vector Multiplications (MVMs) in memory, making them a compelling solution for Machine Learning (ML) workloads. However, existing ML workload partitioning approaches for CIM accelerators do not fully account for Resistive Random Access Memory (RRAM) constraints such as limited memory, high write latency, and limited endurance. They also neglect parallelism, low-level architectural effects, or the Central Processing Unit (CPU) as a complementary compute resource. To address these limitations, we propose an Integer Linear Programming (ILP)-based workload partitioning framework for heterogeneous CPU-CIM systems. It minimizes end-to-end inference latency under RRAM constraints, captures parallelism, and combines empirical profiling with analytical models. Using our framework, heterogeneous CPU-CIM execution achieves speedups of up to 30.9x over CPU-only execution on an edge CPU and 7.3x over a high-performance CPU. A Design Space Exploration (DSE) yields further design insights for future CIM accelerators.
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