arXiv:2607.05814quant-phcs.ET2026-07

用自适应置信门控神经解码,让量子纠错更快更准。

Latency-Constrained Hardware-Aware Quantum Error Correction Co-Design with Adaptive Confidence-Gated Neural Decoding for the Rotated Surface Code

论文配图:Latency-Constrained Hardware-Aware Quantum Error Correction Co-Design with Adaptive Confidence-Gated Neural Decoding for the Rotated Surface Code
图 1 · 摘自论文原文
  • 神经网络快速解码多数测量,低置信度才交由精确算法处理
  • 仅3.3%-6.2%的测量进精修,逻辑错误率从99.21%提至99.81%
  • 可在普通CPU上实现超46万次/秒解码,适合大规模量子系统

实时解码是将噪声中等规模量子(NISQ)设备扩展为容错量子计算的主要瓶颈。本文提出一种针对旋转表面码的自适应置信门控解码框架,将解码视为两阶段推理问题:轻量级前馈神经网络对大多数偶极测量进行快速解码,仅低置信度结果送入最小权重完美匹配(MWPM)精修阶段。我们在电路层去极化噪声下,基于Stim稳定子模拟器对距离 $d \in \{3,5,7,9,11\}$ 的旋转表面码进行评估,分析逻辑保真度、置信度控制下的精度-延迟权衡、解码吞吐量、单次延迟及解码图资源扩展性。仅将3.3%-6.2%的偶极测量路由至精修阶段,即可使逻辑准确率从神经网络基线的99.21%提升至99.81%(置信阈值0.95),且平均解码成本仅小幅增加。神经解码吞吐量在批量大小512时接近 $4.6 \times 10^{5}$ 样本/秒,表明当代码距离 $d > 7$ 后,神经快速路径并非吞吐瓶颈。我们公开完整基准测试流程、训练模型、原始数据及源代码,并明确区分已验证贡献与未来方向,如硬件约束编码发现、GPU加速推理和多噪声优化。

原文摘要 · Abstract (English)

Real-time decoding is a major bottleneck in scaling quantum error correction (QEC) from noisy intermediate-scale quantum (NISQ) devices to fault-tolerant quantum computing. We present an adaptive confidence-gated decoding framework for the rotated surface code that treats decoding as a two-stage inference problem. A lightweight feed-forward neural network performs fast-path decoding for the majority of syndrome measurements, while only low-confidence predictions are escalated to a minimum-weight perfect matching (MWPM) refinement stage. We benchmark the framework on rotated surface codes with distances $d \in \{3,5,7,9,11\}$ under circuit-level depolarising noise using the Stim stabiliser simulator. The evaluation characterises logical accuracy, confidence-controlled accuracy-latency trade-offs, decoding throughput, per-shot latency, and decoding-graph resource scaling. Routing only 3.3%-6.2% of syndromes to the refinement stage improves logical accuracy from 99.21% for the neural-only baseline to 99.81% at a confidence threshold of 0.95 while incurring only a bounded increase in average decoding cost. Neural-decoder throughput saturates near $4.6 \times 10^{5}$ samples s$^{-1}$ at batch size 512 on commodity CPU hardware, indicating that the neural fast path is not the dominant throughput bottleneck beyond code distance $d=7$. We release the complete benchmarking pipeline, trained models, raw benchmark data, and source code, and explicitly distinguish the experimentally validated contributions from the broader hardware-aware QEC co-design roadmap, including hardware-constrained code discovery, GPU-accelerated inference, and multi-noise optimisation, which remain directions for future work.

量子纠错神经解码低延迟硬件协同

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