针对嵌入式FPGA优化图神经网络，降低内存占用同时保持精度
Hardware-aware Graph Neural Networks prunning for embedded event-based vision
- 结合硬件感知剪枝与量化，动态适配资源受限平台
- 在多个数据集上实现26.5%~31.4%的BRAM内存减少
- 适合移动机器人中低功耗实时事件视觉处理场景
事件相机因其在动态环境中的优异表现，正成为移动机器人传感器的首选。然而，这些应用需在低延迟和低功耗下实现实时数据处理。一种有效策略是加速高效算法，并保留事件数据的时间稀疏性。本文提出一种面向嵌入式异构FPGA平台的图卷积神经网络优化方法，结合硬件感知剪枝与量化，权衡片上内存节省与推理精度。通过细粒度网格搜索与贪婪逐层迭代深化搜索，实现模型架构对目标平台的灵活适配。在多种网络结构与多个数据集上的评估表明：在CIFAR-10上减少28.8%的BRAM内存（精度下降1.65%），MNIST-DVS减少31.4%（精度降3.55%），N-Caltech101减少26.5%（精度降5.18%）。
原文摘要 · Abstract (English)
Event-based cameras are gaining popularity as the sensor of choice for mobile robotics, due to their high performance in dynamic environments. However, these applications require efficient real-time data processing with low latency and power consumption. One strategy to meet these stringent requirements is hardware acceleration of efficient algorithms that preserve the temporal sparsity of event data. In this work, we propose an optimization strategy for Graph Convolutional Neural Networks models aimed at adapting their architecture to the limited resources of embedded heterogeneous FPGA platforms. Our method incorporates hardware-aware pruning and quantization, taking into account the trade-off between on-chip memory savings and inference accuracy. Strategic exploration of the design space with Fine Grid Search and Greedy layer-wise Iterative Deepening Search methods enables flexible adaptation of the model architecture to the target platform. Our approach was evaluated across various network configurations and multiple datasets, resulting in BRAM memory reductions of 28.8% for CIFAR-10 (with a 1.65% decrease in accuracy), 31.4% for MNIST-DVS (accuracy drop of 3.55%), and 26.5% for N-Caltech101 (with a 5.18% accuracy reduction).
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