用专家知识约束大模型，自动生成能通过仿真验证的模数转换器
Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation
- 基于电路设计规范构建多步智能体框架，约束大模型生成过程
- 在多个工艺节点上成功生成可仿真通过的逐次逼近型模数转换器
- 适合需要高可靠性模拟电路设计的工程师和自动化研发团队
尽管大语言模型在软件代码生成中表现突出，但在模拟集成电路设计自动化领域仍受限于对电路拓扑理解不足与数据匮乏。直接调用大模型或多模态模型常导致幻觉，无法生成可通过严格SPICE仿真验证的电路图。为此，本文提出端到端、多步骤的智能体框架ATLAS，能够生成功能完整的逐次逼近型模数转换器（SAR ADC），并通过仿真验证。为满足模拟设计的严苛约束，我们引入专家知识，指导模型在规划、元件选择、参数设定及迭代修改各阶段的行为。其中提出的模板约束生成方法，不同于以往模板工作，旨在建立更通用的SAR ADC生成流程。我们在不同工艺节点和输入规格下验证了框架的有效性，证明了基于专家知识的多步智能体框架为可靠模拟设计中的大模型应用奠定了实用基础。
原文摘要 · Abstract (English)
While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked. Owing to limited circuit topology understanding and data, directly prompting LLMs and multimodal models leads to hallucinations and failure to produce schematics capable of passing rigorous SPICE simulations, as we show in our work. Instead, we propose an end-to-end, multi-step LLM agentic framework ATLAS, capable of generating a functional Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that successfully passes simulation validation. To adhere to the rigid constraints of analog design, we utilize expert knowledge to ground the LLM in its planning, selection, parameterization, and iterative modification. As part of ATLAS, we introduce Template-Constrained Generation - which unlike other template-based works - builds towards a more generalized SAR ADC generation flow. We demonstrate a strong proof-of-concept of our framework by developing SAR ADCs across technology nodes and input specs. Overall, our expert-knowledge grounded multi-step agentic ATLAS establishes a pragmatic foundation for integrating LLMs into reliable analog design methodologies.
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