提出动态精度量化与流水线硬件,提升嵌入式系统安全性与能效。
Lazy Arithmetic using Systolic Arrays for Closing the Verification Gap on Embedded Systems

- 左到右计算先传高位位,动态调整精度并分析风险。
- 硬件用流水阵列实现高位优先计算,抗位翻转攻击。
- 适合医疗等安全关键场景的低功耗高可靠计算。
深度神经网络等复杂算法正越来越多部署于资源受限的嵌入式平台,但现有软硬件方案在安全关键应用(如医疗设备)中仍存在不足。硬件如GPU、NPU、TPU侧重吞吐量而非计算正确性,易受故障注入攻击;软件量化方案或静态可靠但功耗高,或动态但不可靠。为此,本文提出一种实时、动态且可靠的自适应精度量化方法,利用左到右算术先传输最高有效位(MSB),在线动态调整精度,并通过敏感性分析量化决策边界穿越风险。同时,设计新型流水阵列硬件实现左到右算术,优先生成高位。该方案不仅支持边缘端高效神经网络计算,更可广泛用于高精度数学运算,确保对关键位翻转攻击的鲁棒性。目前软件实现已完成,硬件仍在开发中。
原文摘要 · Abstract (English)
Complex algorithms such as deep neural networks are increasingly being deployed on embedded, resource constrained platforms. However, existing hardware and software schemes for implementing these models on the edge fall short, particularly for safety-critical applications such as medical devices. First, hardware such as GPUs, NPUs and TPUs are designed for throughput rather than correctness of computation of security, and are as such susceptible to fault injection attacks. Second, software schemes designed for porting algorithms onto edge devices -- such as quantization schemes -- are either static and sound (non-optimal power consumption), or dynamic yet unsound (non-optimal for safety-critical applications). To address both these needs we propose a both wholly new approach to real-time, dynamic and sound quantization, as well as the hardware to support it. First we developed a sound, real-time adaptive-precision quantization approach utilizing left-to-right arithmetic to pass the most significant bits (MSB) first, and dynamically adjust precision online while performing sensitivity analysis to quantify and manage the risk of decision-boundary crossings. Next, we propose a novel hardware approach utilizing systolic arrays to perform left-to-right arithmetic to generate the MSB first. Together this provides a wholly novel scheme for enabling not only resource-efficient neural networks and artificial intelligence at the edge, but broadly sound and resource-efficient high-precision mathematics on hardware that ensures resilience to bit flip attacks on the most critical bits. This is presented herein as work-in-progress, with software implementations completed and hardware in-progress.
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